From: mason.huo <mason.huo@starfivetech.com>
Date: Mon, 24 Oct 2022 08:51:24 +0000 (+0800)
Subject: riscv: dts: starfive: Remove unsupported cpu frequencies
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=932b1936ca9d23e91f3a068fb429ff4cb603a17a;p=platform%2Fkernel%2Flinux-starfive.git

riscv: dts: starfive: Remove unsupported cpu frequencies

As the pll0 is fixed, there are only four cpu frequencies
that can be divided from the pll0, so remove the other
cpu frequencies.

Signed-off-by: mason.huo <mason.huo@starfivetech.com>
---

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 99db7b0cafd4..3c5383501bda 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -28,41 +28,13 @@
 					opp-hz = /bits/ 64 <500000000>;
 					opp-microvolt = <880000>;
 			};
-			opp-625000000 {
-					opp-hz = /bits/ 64 <625000000>;
-					opp-microvolt = <880000>;
-			};
 			opp-750000000 {
 					opp-hz = /bits/ 64 <750000000>;
 					opp-microvolt = <880000>;
 			};
-			opp-875000000 {
-					opp-hz = /bits/ 64 <875000000>;
-					opp-microvolt = <880000>;
-			};
-			opp-1000000000 {
-					opp-hz = /bits/ 64 <1000000000>;
-					opp-microvolt = <900000>;
-			};
-			opp-1250000000 {
-					opp-hz = /bits/ 64 <1250000000>;
-					opp-microvolt = <950000>;
-			};
-			opp-1375000000 {
-					opp-hz = /bits/ 64 <1375000000>;
-					opp-microvolt = <1000000>;
-			};
 			opp-1500000000 {
 					opp-hz = /bits/ 64 <1500000000>;
-					opp-microvolt = <1100000>;
-			};
-			opp-1625000000 {
-					opp-hz = /bits/ 64 <1625000000>;
-					opp-microvolt = <1100000>;
-			};
-			opp-1750000000 {
-					opp-hz = /bits/ 64 <1750000000>;
-					opp-microvolt = <1200000>;
+					opp-microvolt = <1000000>;
 			};
 	};
 
@@ -1808,10 +1780,8 @@
 
 		starfive_cpufreq: starfive,jh7110-cpufreq {
 			compatible = "starfive,jh7110-cpufreq";
-			clocks = <&clkgen JH7110_PLL0_OUT>,
-					 <&clkgen JH7110_CPU_ROOT>,
-					 <&osc>;
-			clock-names = "pll0", "cpu_clk", "osc";
+			clocks = <&clkgen JH7110_CPU_CORE>;
+			clock-names = "cpu_clk";
 		};
 	};
 };