From: Kenneth Graunke Date: Tue, 14 Dec 2021 00:46:23 +0000 (-0800) Subject: intel/vec4: Use nir_texop in emit_texture instead of translating X-Git-Tag: upstream/22.3.5~14719 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=92d194427da7ed2c74280f7e5b0dc4789bb0b537;p=platform%2Fupstream%2Fmesa.git intel/vec4: Use nir_texop in emit_texture instead of translating We eliminated the GLSL IR -> vec4 backend ages ago, so the only caller uses a nir_texop enum. Drop a layer of translating. Reviewed-by: Caio Oliveira Part-of: --- diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h index 40889d9..3906f71 100644 --- a/src/intel/compiler/brw_vec4.h +++ b/src/intel/compiler/brw_vec4.h @@ -254,7 +254,7 @@ public: void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0); void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0); - void emit_texture(ir_texture_opcode op, + void emit_texture(nir_texop op, dst_reg dest, int dest_components, src_reg coordinate, diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 7dc56f6..9359452 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1944,31 +1944,6 @@ vec4_visitor::nir_emit_jump(nir_jump_instr *instr) } } -static enum ir_texture_opcode -ir_texture_opcode_for_nir_texop(nir_texop texop) -{ - enum ir_texture_opcode op; - - switch (texop) { - case nir_texop_lod: op = ir_lod; break; - case nir_texop_query_levels: op = ir_query_levels; break; - case nir_texop_texture_samples: op = ir_texture_samples; break; - case nir_texop_tex: op = ir_tex; break; - case nir_texop_tg4: op = ir_tg4; break; - case nir_texop_txb: op = ir_txb; break; - case nir_texop_txd: op = ir_txd; break; - case nir_texop_txf: op = ir_txf; break; - case nir_texop_txf_ms: op = ir_txf_ms; break; - case nir_texop_txl: op = ir_txl; break; - case nir_texop_txs: op = ir_txs; break; - case nir_texop_samples_identical: op = ir_samples_identical; break; - default: - unreachable("unknown texture opcode"); - } - - return op; -} - void vec4_visitor::nir_emit_texture(nir_tex_instr *instr) { @@ -2108,9 +2083,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr) } } - ir_texture_opcode op = ir_texture_opcode_for_nir_texop(instr->op); - - emit_texture(op, dest, nir_tex_instr_dest_size(instr), + emit_texture(instr->op, dest, nir_tex_instr_dest_size(instr), coordinate, instr->coord_components, shadow_comparator, lod, lod2, sample_index, diff --git a/src/intel/compiler/brw_vec4_visitor.cpp b/src/intel/compiler/brw_vec4_visitor.cpp index 53adb49..ba6b283 100644 --- a/src/intel/compiler/brw_vec4_visitor.cpp +++ b/src/intel/compiler/brw_vec4_visitor.cpp @@ -826,7 +826,7 @@ vec4_visitor::is_high_sampler(src_reg sampler) } void -vec4_visitor::emit_texture(ir_texture_opcode op, +vec4_visitor::emit_texture(nir_texop op, dst_reg dest, int dest_components, src_reg coordinate, @@ -843,27 +843,28 @@ vec4_visitor::emit_texture(ir_texture_opcode op, { enum opcode opcode; switch (op) { - case ir_tex: opcode = SHADER_OPCODE_TXL; break; - case ir_txl: opcode = SHADER_OPCODE_TXL; break; - case ir_txd: opcode = SHADER_OPCODE_TXD; break; - case ir_txf: opcode = SHADER_OPCODE_TXF; break; - case ir_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break; - case ir_txs: opcode = SHADER_OPCODE_TXS; break; - case ir_tg4: opcode = offset_value.file != BAD_FILE - ? SHADER_OPCODE_TG4_OFFSET : SHADER_OPCODE_TG4; break; - case ir_query_levels: opcode = SHADER_OPCODE_TXS; break; - case ir_texture_samples: opcode = SHADER_OPCODE_SAMPLEINFO; break; - case ir_txb: - unreachable("TXB is not valid for vertex shaders."); - case ir_lod: - unreachable("LOD is not valid for vertex shaders."); - case ir_samples_identical: { + case nir_texop_tex: opcode = SHADER_OPCODE_TXL; break; + case nir_texop_txl: opcode = SHADER_OPCODE_TXL; break; + case nir_texop_txd: opcode = SHADER_OPCODE_TXD; break; + case nir_texop_txf: opcode = SHADER_OPCODE_TXF; break; + case nir_texop_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break; + case nir_texop_txs: opcode = SHADER_OPCODE_TXS; break; + case nir_texop_query_levels: opcode = SHADER_OPCODE_TXS; break; + case nir_texop_texture_samples: opcode = SHADER_OPCODE_SAMPLEINFO; break; + case nir_texop_tg4: + opcode = offset_value.file != BAD_FILE ? SHADER_OPCODE_TG4_OFFSET + : SHADER_OPCODE_TG4; + break; + case nir_texop_samples_identical: { /* There are some challenges implementing this for vec4, and it seems * unlikely to be used anyway. For now, just return false ways. */ emit(MOV(dest, brw_imm_ud(0u))); return; } + case nir_texop_txb: + case nir_texop_lod: + unreachable("Implicit LOD is only valid inside fragment shaders."); default: unreachable("Unrecognized tex op"); } @@ -1019,17 +1020,17 @@ vec4_visitor::emit_texture(ir_texture_opcode op, /* fixup num layers (z) for cube arrays: hardware returns faces * layers; * spec requires layers. */ - if (op == ir_txs && devinfo->ver < 7) { + if (op == nir_texop_txs && devinfo->ver < 7) { /* Gfx4-6 return 0 instead of 1 for single layer surfaces. */ emit_minmax(BRW_CONDITIONAL_GE, writemask(inst->dst, WRITEMASK_Z), src_reg(inst->dst), brw_imm_d(1)); } - if (devinfo->ver == 6 && op == ir_tg4) { + if (devinfo->ver == 6 && op == nir_texop_tg4) { emit_gfx6_gather_wa(key_tex->gfx6_gather_wa[surface], inst->dst); } - if (op == ir_query_levels) { + if (op == nir_texop_query_levels) { /* # levels is in .w */ src_reg swizzled(dest); swizzled.swizzle = BRW_SWIZZLE4(SWIZZLE_W, SWIZZLE_W,