From: Samuel Pitoiset Date: Wed, 6 Jan 2016 17:46:00 +0000 (+0100) Subject: nvc0: bind shader buffers for compute on Fermi X-Git-Tag: upstream/17.1.0~12381 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=917a5ff6eac8e000e1ac7041929ae376bd476496;p=platform%2Fupstream%2Fmesa.git nvc0: bind shader buffers for compute on Fermi This is loosely based on 3D. Shader buffers are bound on c15 (the driver constbuf) at offset 0x200. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c index 2314c53..83768a2 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c @@ -212,6 +212,38 @@ nvc0_compute_validate_driverconst(struct nvc0_context *nvc0) nvc0->dirty |= NVC0_NEW_DRIVERCONST; } +static void +nvc0_compute_validate_buffers(struct nvc0_context *nvc0) +{ + struct nouveau_pushbuf *push = nvc0->base.pushbuf; + const int s = 5; + int i; + + BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3); + PUSH_DATA (push, 1024); + PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (6 << 16) + (s << 10)); + PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (6 << 16) + (s << 10)); + BEGIN_1IC0(push, NVC0_COMPUTE(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS); + PUSH_DATA (push, 512); + + for (i = 0; i < NVC0_MAX_BUFFERS; i++) { + if (nvc0->buffers[s][i].buffer) { + struct nv04_resource *res = + nv04_resource(nvc0->buffers[s][i].buffer); + PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset); + PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset); + PUSH_DATA (push, nvc0->buffers[s][i].buffer_size); + PUSH_DATA (push, 0); + BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR); + } else { + PUSH_DATA (push, 0); + PUSH_DATA (push, 0); + PUSH_DATA (push, 0); + PUSH_DATA (push, 0); + } + } +} + static bool nvc0_compute_state_validate(struct nvc0_context *nvc0) { @@ -221,6 +253,8 @@ nvc0_compute_state_validate(struct nvc0_context *nvc0) nvc0_compute_validate_constbufs(nvc0); if (nvc0->dirty_cp & NVC0_NEW_CP_DRIVERCONST) nvc0_compute_validate_driverconst(nvc0); + if (nvc0->dirty_cp & NVC0_NEW_CP_BUFFERS) + nvc0_compute_validate_buffers(nvc0); /* TODO: textures, samplers, surfaces, global memory buffers */ diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c index 3d2ed75..66e7f95 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c @@ -261,12 +261,17 @@ nvc0_invalidate_resource_storage(struct nouveau_context *ctx, } } - for (s = 0; s < 5; ++s) { + for (s = 0; s < 6; ++s) { for (i = 0; i < NVC0_MAX_BUFFERS; ++i) { if (nvc0->buffers[s][i].buffer == res) { nvc0->buffers_dirty[s] |= 1 << i; - nvc0->dirty |= NVC0_NEW_BUFFERS; - nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF); + if (unlikely(s == 5)) { + nvc0->dirty_cp |= NVC0_NEW_CP_BUFFERS; + nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF); + } else { + nvc0->dirty |= NVC0_NEW_BUFFERS; + nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF); + } if (!--ref) return ref; } diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h index 86116a0..2b5ab73 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h @@ -66,6 +66,7 @@ #define NVC0_NEW_CP_CONSTBUF (1 << 4) #define NVC0_NEW_CP_GLOBALS (1 << 5) #define NVC0_NEW_CP_DRIVERCONST (1 << 6) +#define NVC0_NEW_CP_BUFFERS (1 << 7) /* 3d bufctx (during draw_vbo, blit_3d) */ #define NVC0_BIND_FB 0 @@ -89,7 +90,8 @@ #define NVC0_BIND_CP_DESC 50 #define NVC0_BIND_CP_SCREEN 51 #define NVC0_BIND_CP_QUERY 52 -#define NVC0_BIND_CP_COUNT 53 +#define NVC0_BIND_CP_BUF 53 +#define NVC0_BIND_CP_COUNT 54 /* bufctx for other operations */ #define NVC0_BIND_2D 0 diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c index afcff53..bc884d6 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c @@ -546,6 +546,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset, info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0); } else { info->io.resInfoCBSlot = 15; + info->io.suInfoBase = 512; } info->io.msInfoCBSlot = 0; info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c index 157d628..9391ad6 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c @@ -1245,7 +1245,7 @@ nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t, const unsigned mask = ((1 << nr) - 1) << start; unsigned i; - assert(t < 5); + assert(t < 6); if (pbuffers) { for (i = start; i < end; ++i) { @@ -1265,7 +1265,11 @@ nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t, } nvc0->buffers_dirty[t] |= mask; - nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF); + if (t == 5) + nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF); + else + nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF); + } static void @@ -1277,7 +1281,10 @@ nvc0_set_shader_buffers(struct pipe_context *pipe, const unsigned s = nvc0_shader_stage(shader); nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers); - nvc0_context(pipe)->dirty |= NVC0_NEW_BUFFERS; + if (s == 5) + nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS; + else + nvc0_context(pipe)->dirty |= NVC0_NEW_BUFFERS; } static inline void