From: Anson Huang Date: Wed, 20 May 2020 06:30:16 +0000 (+0800) Subject: ARM: dts: imx: Make tempmon node as child of anatop node X-Git-Tag: v5.15~3247^2~42^2~40 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=915e19686f5991bf6dd9160ef6830041083c894f;p=platform%2Fkernel%2Flinux-starfive.git ARM: dts: imx: Make tempmon node as child of anatop node i.MX6/7 SoCs' temperature sensor is inside anatop module from HW perspective, so it should be a child node of anatop. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 32114cf..642054bb 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -69,17 +69,6 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - #thermal-sensor-cells = <0>; - }; - ldb: ldb { #address-cells = <1>; #size-cells = <0>; @@ -795,6 +784,17 @@ anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; }; + + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; + }; }; usbphy1: usbphy@20c9000 { diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 911d8cf..d8efc0a 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -93,16 +93,6 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; - }; - pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&gpc>; @@ -628,6 +618,16 @@ anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; }; + + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; + }; }; usbphy1: usbphy@20c9000 { diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index edd3abb..bf7f048 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -105,16 +105,6 @@ clock-output-names = "ipp_di1"; }; - tempmon: temperature-sensor { - compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; - interrupts = ; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -531,6 +521,16 @@ anatop-max-voltage = <3400000>; anatop-enable-bit = <0>; }; + + tempmon: temperature-sensor { + compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; + }; }; usbphy1: usb-phy@20c9000 { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 94e3df4..ddcbfce 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -134,16 +134,6 @@ clock-output-names = "anaclk2"; }; - tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; - }; - pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&gpc>; @@ -696,6 +686,16 @@ anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; }; + + tempmon: tempmon { + compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + }; }; usbphy1: usbphy@20c9000 { diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 5379a03..6575937 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -131,16 +131,6 @@ clock-output-names = "ipp_di1"; }; - tempmon: tempmon { - compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; - }; - pmu { compatible = "arm,cortex-a7-pmu"; interrupt-parent = <&gpc>; @@ -612,6 +602,16 @@ anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; }; + + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; }; usbphy1: usbphy@20c9000 { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index f6bb35d..ddf8b81 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -147,16 +147,6 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx7d-tempmon"; - interrupt-parent = <&gpc>; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&fuse_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; - }; - timer { compatible = "arm,armv7-timer"; interrupt-parent = <&intc>; @@ -586,6 +576,16 @@ anatop-max-voltage = <1300000>; anatop-enable-bit = <0>; }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&fuse_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + }; }; snvs: snvs@30370000 {