From: Wu, Hao <hao.wu@intel.com>
Date: Tue, 31 Jan 2012 05:02:43 +0000 (+0800)
Subject: usb/penwell_otg: disable PHY interrupt VBUSVALID/ID when connect to Host
X-Git-Tag: 2.1b_release~1448
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=90f21c5d88368dad19359f4878bfdb571c66a59b;p=platform%2Fkernel%2Fkernel-mfld-blackbay.git

usb/penwell_otg: disable PHY interrupt VBUSVALID/ID when connect to Host

BZ: 22901

This is a workaround patch in penwell_otg driver, disable PHY interrupt
VBUSVALID and ID when connected to a USB Host to avoid unexpected RxCMD
from PHY, this is for MFLD only.

Change-Id: I6d80a2b5d3d5b91a7a49685b0d1fb0afb7b1df41
Signed-off-by: Wu, Hao <hao.wu@intel.com>
Reviewed-on: http://android.intel.com:8080/34495
Reviewed-by: Tang, Richard <richard.tang@intel.com>
Reviewed-by: Meng, Zhe <zhe.meng@intel.com>
Tested-by: Meng, Zhe <zhe.meng@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
---

diff --git a/drivers/usb/otg/penwell_otg.c b/drivers/usb/otg/penwell_otg.c
index 20a21ea..791f22c 100644
--- a/drivers/usb/otg/penwell_otg.c
+++ b/drivers/usb/otg/penwell_otg.c
@@ -1450,6 +1450,44 @@ void penwell_otg_phy_vbus_wakeup(bool on)
 	dev_dbg(pnw->dev, "%s --->\n", __func__);
 }
 
+void penwell_otg_phy_intr(bool on)
+{
+	struct penwell_otg	*pnw = the_transceiver;
+	u8			flag = 0;
+	int			retval;
+	u8			data;
+
+	dev_dbg(pnw->dev, "%s --->\n", __func__);
+
+	penwell_otg_msic_spi_access(true);
+
+	flag = VBUSVLD | IDGND;
+
+	if (on) {
+		dev_info(pnw->dev, "enable VBUSVLD & IDGND\n");
+		penwell_otg_msic_write(MSIC_USBINTEN_RISESET, flag);
+		penwell_otg_msic_write(MSIC_USBINTEN_FALLSET, flag);
+	} else {
+		dev_info(pnw->dev, "disable VBUSVLD & IDGND\n");
+		penwell_otg_msic_write(MSIC_USBINTEN_RISECLR, flag);
+		penwell_otg_msic_write(MSIC_USBINTEN_FALLCLR, flag);
+	}
+
+	retval = intel_scu_ipc_ioread8(MSIC_USBINTEN_RISE, &data);
+	if (retval)
+		dev_warn(pnw->dev, "Failed to read MSIC register\n");
+	else
+		dev_info(pnw->dev, "MSIC_USBINTEN_RISE = 0x%x", data);
+
+	retval = intel_scu_ipc_ioread8(MSIC_USBINTEN_FALL, &data);
+	if (retval)
+		dev_warn(pnw->dev, "Failed to read MSIC register\n");
+	else
+		dev_info(pnw->dev, "MSIC_USBINTEN_FALL = 0x%x", data);
+
+	penwell_otg_msic_spi_access(false);
+}
+
 void penwell_otg_nsf_msg(unsigned long indicator)
 {
 	switch (indicator) {
@@ -2234,6 +2272,13 @@ static void penwell_otg_work(struct work_struct *work)
 			} else if (charger_type == CHRG_CDP) {
 				dev_info(pnw->dev, "CDP detected\n");
 
+				/* MFLD WA: MSIC issue need disable phy intr */
+				if (!is_clovertrail(pdev)) {
+					dev_dbg(pnw->dev,
+						"MFLD WA: enable PHY int\n");
+					penwell_otg_phy_intr(0);
+				}
+
 				/* CDP: set charger type, current, notify EM */
 				penwell_otg_update_chrg_cap(CHRG_CDP,
 							CHRG_CURR_CDP);
@@ -2252,6 +2297,13 @@ static void penwell_otg_work(struct work_struct *work)
 			} else if (charger_type == CHRG_SDP) {
 				dev_info(pnw->dev, "SDP detected\n");
 
+				/* MFLD WA: MSIC issue need disable phy intr */
+				if (!is_clovertrail(pdev)) {
+					dev_dbg(pnw->dev,
+						"MFLD WA: enable PHY int\n");
+					penwell_otg_phy_intr(0);
+				}
+
 				/* SDP: set charger type */
 				penwell_otg_update_chrg_cap(CHRG_SDP,
 							pnw->charging_cap.mA);
@@ -2376,6 +2428,12 @@ static void penwell_otg_work(struct work_struct *work)
 				dev_dbg(pnw->dev,
 					"client driver has been removed.\n");
 
+			/* MFLD WA: reenable it for unplug event */
+			if (!is_clovertrail(pdev)) {
+				dev_dbg(pnw->dev, "MFLD WA: disable PHY int\n");
+				penwell_otg_phy_intr(1);
+			}
+
 			iotg->otg.state = OTG_STATE_B_IDLE;
 		} else if (hsm->b_bus_req && hsm->a_bus_suspend
 				&& iotg->otg.gadget