From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 13 Nov 2017 01:47:52 +0000 (+0000)
Subject: Fix some misc. -enable-var-scope violations
X-Git-Tag: llvmorg-6.0.0-rc1~3585
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=90e4f719e1d372ec9a667b3346247c48d13bfde9;p=platform%2Fupstream%2Fllvm.git

Fix some misc. -enable-var-scope violations

llvm-svn: 318006
---

diff --git a/llvm/test/CodeGen/AArch64/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/arm64-atomic.ll
index 2c9a3bb..db343e9 100644
--- a/llvm/test/CodeGen/AArch64/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-atomic.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck -enable-var-scope %s
 
 define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
 ; CHECK-LABEL: val_compare_and_swap:
@@ -22,16 +22,16 @@ define i32 @val_compare_and_swap_from_load(i32* %p, i32 %cmp, i32* %pnew) #0 {
 ; CHECK-LABEL: val_compare_and_swap_from_load:
 ; CHECK-NEXT: ldr    [[NEW:w[0-9]+]], [x2]
 ; CHECK-NEXT: [[TRYBB:.?LBB[0-9_]+]]:
-; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x0]
-; CHECK-NEXT: cmp    [[RESULT]], w1
+; CHECK-NEXT: ldaxr  w[[RESULT:[0-9]+]], [x0]
+; CHECK-NEXT: cmp    w[[RESULT]], w1
 ; CHECK-NEXT: b.ne   [[FAILBB:.?LBB[0-9_]+]]
 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0]
 ; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[TRYBB]]
-; CHECK-NEXT: mov    x0, x[[ADDR]]
+; CHECK-NEXT: mov    x0, x[[RESULT]]
 ; CHECK-NEXT: ret
 ; CHECK-NEXT: [[FAILBB]]:
 ; CHECK-NEXT: clrex
-; CHECK-NEXT: mov    x0, x[[ADDR]]
+; CHECK-NEXT: mov    x0, x[[RESULT]]
 ; CHECK-NEXT: ret
   %new = load i32, i32* %pnew
   %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
diff --git a/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll b/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
index a104b65..3d23dcd 100644
--- a/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
@@ -1,6 +1,6 @@
-; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
-; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
-; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=DISABLE
 
 ; CodeGenPrepare should move the zext into the block with the load
 ; so that SelectionDAG can select it with the load.
@@ -81,8 +81,8 @@ false:
 ; #1 will not be removed as we do not know anything about %b.
 ; #2 may not be merged with the load because %t is used in a comparison.
 ; Since two extensions may be emitted in the end instead of one before the
-; transformation, the regular heuristic does not apply the optimization. 
-; 
+; transformation, the regular heuristic does not apply the optimization.
+;
 ; OPTALL-LABEL: @promoteTwoArgZext
 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ;
@@ -637,12 +637,12 @@ define i64 @doNotPromoteBecauseOfPairedLoad(i32* %p, i32 %cst) {
 define i64 @promoteZextShl(i1 %c, i16* %P) {
 entry:
 ; OPTALL-LABEL: promoteZextShl
-; OPTALL-LABEL: entry:
+; OPTALL: entry:
 ; OPT: %[[LD:.*]] = load i16, i16* %P
 ; OPT: %[[EXT:.*]] = zext i16 %[[LD]] to i64
-; OPT-LABEL: if.then:
+; OPT: if.then:
 ; OPT: shl nsw i64 %[[EXT]], 1
-; DISABLE-LABEL: if.then:
+; DISABLE: if.then:
 ; DISABLE: %r = sext i32 %shl2 to i64
   %ld = load i16, i16* %P
   br i1 %c, label %end, label %if.then
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index 164351e..2ae0da2 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone -aarch64-enable-atomic-cfg-tidy=0 < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone -aarch64-enable-atomic-cfg-tidy=0 < %s | FileCheck -enable-var-scope %s
 
 @lhs = global fp128 zeroinitializer, align 16
 @rhs = global fp128 zeroinitializer, align 16
@@ -262,7 +262,7 @@ define void @test_extend() {
 }
 
 define fp128 @test_neg(fp128 %in) {
-; CHECK: [[MINUS0:.LCPI[0-9]+_0]]:
+; CHECK: [[$MINUS0:.LCPI[0-9]+_0]]:
 ; Make sure the weird hex constant below *is* -0.0
 ; CHECK-NEXT: fp128 -0
 
@@ -272,7 +272,7 @@ define fp128 @test_neg(fp128 %in) {
   ; sure that doesn't happen.
   %ret = fsub fp128 0xL00000000000000008000000000000000, %in
 ; CHECK: mov v1.16b, v0.16b
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:[[MINUS0]]]
+; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:[[$MINUS0]]]
 ; CHECK: bl __subtf3
 
   ret fp128 %ret
diff --git a/llvm/test/CodeGen/AArch64/arm64-scvt.ll b/llvm/test/CodeGen/AArch64/arm64-scvt.ll
index 4697e1f..d886d7c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-scvt.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-scvt.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s
+; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck -enable-var-scope %s
+; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck -enable-var-scope --check-prefix=CHECK-A57 %s
 ; rdar://13082402
 
 define float @t1(i32* nocapture %src) nounwind ssp {
@@ -439,7 +439,7 @@ entry:
 define float @sfct3(i32* nocapture %sp0) {
 ; CHECK-LABEL: sfct3:
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 1
@@ -500,7 +500,7 @@ entry:
 define float @sfct7(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct7:
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 %offset
@@ -574,7 +574,7 @@ entry:
 define double @sfct12(i64* nocapture %sp0) {
 ; CHECK-LABEL: sfct12:
 ; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 1
@@ -634,7 +634,7 @@ entry:
 define double @sfct16(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct16:
 ; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 %offset
@@ -684,7 +684,7 @@ define float @sfct18(i16* nocapture %sp0) {
 define float @sfct19(i32* nocapture %sp0) {
 ; CHECK-LABEL: sfct19:
 ; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
@@ -765,7 +765,7 @@ define double @sfct23(i32* nocapture %sp0) {
 define double @sfct24(i64* nocapture %sp0) {
 ; CHECK-LABEL: sfct24:
 ; CHECK: ldur d[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll
index c3c11a1..972cffe 100644
--- a/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll
@@ -1,24 +1,24 @@
-; RUN: opt -S -codegenprepare -mtriple=aarch64-linux %s | FileCheck %s
+; RUN: opt -S -codegenprepare -mtriple=aarch64-linux %s | FileCheck -enable-var-scope %s
 
 ; Test for CodeGenPrepare::optimizeLoadExt(): simple case: two loads
 ; feeding a phi that zext's each loaded value.
 define i32 @test_free_zext(i32* %ptr, i32* %ptr2, i32 %c) {
 ; CHECK-LABEL: @test_free_zext(
 bb1:
-; CHECK-LABEL: bb1:
+; CHECK: bb1:
 ; CHECK: %[[T1:.*]] = load
 ; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535
   %load1 = load i32, i32* %ptr, align 4
   %cmp = icmp ne i32 %c, 0
   br i1 %cmp, label %bb2, label %bb3
 bb2:
-; CHECK-LABEL: bb2:
+; CHECK: bb2:
 ; CHECK: %[[T2:.*]] = load
 ; CHECK: %[[A2:.*]] = and i32 %[[T2]], 65535
   %load2 = load i32, i32* %ptr2, align 4
   br label %bb3
 bb3:
-; CHECK-LABEL: bb3:
+; CHECK: bb3:
 ; CHECK: phi i32 [ %[[A1]], %bb1 ], [ %[[A2]], %bb2 ]
   %phi = phi i32 [ %load1, %bb1 ], [ %load2, %bb2 ]
   %and = and i32 %phi, 65535
@@ -30,24 +30,24 @@ bb3:
 define i32 @test_free_zext2(i32* %ptr, i16* %dst16, i32* %dst32, i32 %c) {
 ; CHECK-LABEL: @test_free_zext2(
 bb1:
-; CHECK-LABEL: bb1:
+; CHECK: bb1:
 ; CHECK: %[[T1:.*]] = load
 ; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535
   %load1 = load i32, i32* %ptr, align 4
   %cmp = icmp ne i32 %c, 0
   br i1 %cmp, label %bb2, label %bb4
 bb2:
-; CHECK-LABEL: bb2:
+; CHECK: bb2:
   %trunc = trunc i32 %load1 to i16
   store i16 %trunc, i16* %dst16, align 2
   br i1 %cmp, label %bb3, label %bb4
 bb3:
-; CHECK-LABEL: bb3:
+; CHECK: bb3:
   %shl = shl i32 %load1, 16
   store i32 %shl, i32* %dst32, align 4
   br label %bb4
 bb4:
-; CHECK-LABEL: bb4:
+; CHECK: bb4:
 ; CHECK-NOT: and
 ; CHECK: ret i32 %[[A1]]
   %and = and i32 %load1, 65535
@@ -59,21 +59,21 @@ bb4:
 define void @test_free_zext3(i32* %ptr, i32* %ptr2, i32* %dst, i64* %c) {
 ; CHECK-LABEL: @test_free_zext3(
 bb1:
-; CHECK-LABEL: bb1:
+; CHECK: bb1:
 ; CHECK: %[[T1:.*]] = load
 ; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535
   %load1 = load i32, i32* %ptr, align 4
   br label %loop
 loop:
-; CHECK-LABEL: loop:
-; CHECK: phi i32 [ %[[A1]], %bb1 ], [ %[[A2]], %loop ]
+; CHECK: loop:
+; CHECK: phi i32 [ %[[A1]], %bb1 ], [ %[[A2:.*]], %loop ]
   %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ]
   %and = and i32 %phi, 65535
   store i32 %and, i32* %dst, align 4
   %idx = load volatile i64, i64* %c, align 4
   %addr = getelementptr inbounds i32, i32* %ptr2, i64 %idx
 ; CHECK: %[[T2:.*]] = load i32
-; CHECK: %[[A2:.*]] = and i32 %[[T2]], 65535
+; CHECK: %[[A2]] = and i32 %[[T2]], 65535
   %load2 = load i32, i32* %addr, align 4
   %cmp = icmp ne i64 %idx, 0
   br i1 %cmp, label %loop, label %end
diff --git a/llvm/test/Transforms/InstCombine/cast-call-combine-prof.ll b/llvm/test/Transforms/InstCombine/cast-call-combine-prof.ll
index 05b71b6..510473e 100644
--- a/llvm/test/Transforms/InstCombine/cast-call-combine-prof.ll
+++ b/llvm/test/Transforms/InstCombine/cast-call-combine-prof.ll
@@ -1,4 +1,4 @@
-; RUN: opt -S -instcombine < %s | FileCheck %s
+; RUN: opt -S -instcombine < %s | FileCheck -enable-var-scope %s
 
 ; Check that instcombine preserves !prof metadata when removing function
 ; prototype casts.
@@ -8,7 +8,7 @@ declare void @__cxa_call_unexpected(i8*)
 declare void @foo(i16* %a)
 
 ; CHECK-LABEL: @test_call()
-; CHECK: call void @foo(i16* null), !prof ![[PROF:[0-9]+]]
+; CHECK: call void @foo(i16* null), !prof ![[$PROF:[0-9]+]]
 define void @test_call() {
   call void bitcast (void (i16*)* @foo to void (i8*)*) (i8* null), !prof !0
   ret void
@@ -16,7 +16,7 @@ define void @test_call() {
 
 ; CHECK-LABEL: @test_invoke()
 ; CHECK: invoke void @foo(i16* null)
-; CHECK-NEXT: to label %done unwind label %lpad, !prof ![[PROF]]
+; CHECK-NEXT: to label %done unwind label %lpad, !prof ![[$PROF]]
 define void @test_invoke() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
   invoke void bitcast (void (i16*)* @foo to void (i8*)*) (i8* null)
           to label %done unwind label %lpad, !prof !0
@@ -32,7 +32,7 @@ lpad:
   unreachable
 }
 
-; CHECK: ![[PROF]] = !{!"branch_weights", i32 2000}
+; CHECK: ![[$PROF]] = !{!"branch_weights", i32 2000}
 !0 = !{!"VP", i32 0, i64 2000, i64 -3913987384944532146, i64 2000}
 
 !llvm.module.flags = !{!1}
diff --git a/llvm/test/Transforms/InstCombine/convergent.ll b/llvm/test/Transforms/InstCombine/convergent.ll
index 9b9ae6f..1791de7 100644
--- a/llvm/test/Transforms/InstCombine/convergent.ll
+++ b/llvm/test/Transforms/InstCombine/convergent.ll
@@ -1,4 +1,4 @@
-; RUN: opt -instcombine -S < %s | FileCheck %s
+; RUN: opt -instcombine -S < %s | FileCheck -enable-var-scope %s
 
 declare i32 @k() convergent
 declare i32 @f()
@@ -7,7 +7,7 @@ declare i64 @llvm.read_register.i64(metadata) nounwind
 
 define i32 @extern() {
   ; Convergent attr shouldn't be removed here; k is convergent.
-  ; CHECK: call i32 @k() [[CONVERGENT_ATTR:#[0-9]+]]
+  ; CHECK: call i32 @k() [[$CONVERGENT_ATTR:#[0-9]+]]
   %a = call i32 @k() convergent
   ret i32 %a
 }
@@ -27,18 +27,18 @@ define i32 @no_extern() {
 }
 
 define i32 @indirect_call(i32 ()* %f) {
-  ; CHECK: call i32 %f() [[CONVERGENT_ATTR]]
+  ; CHECK: call i32 %f() [[$CONVERGENT_ATTR]]
   %a = call i32 %f() convergent
   ret i32 %a
 }
 
 ; do not remove from convergent intrinsic call sites
 ; CHECK-LABEL: @convergent_intrinsic_call(
-; CHECK: call i64 @llvm.read_register.i64(metadata !0) [[CONVERGENT_ATTR]]
+; CHECK: call i64 @llvm.read_register.i64(metadata !0) [[$CONVERGENT_ATTR]]
 define i64 @convergent_intrinsic_call() {
   %val = call i64 @llvm.read_register.i64(metadata !0) convergent
   ret i64 %val
 }
 
-; CHECK: [[CONVERGENT_ATTR]] = { convergent }
+; CHECK: [[$CONVERGENT_ATTR]] = { convergent }
 !0 = !{!"foo"}
diff --git a/llvm/test/Transforms/InstCombine/ctpop.ll b/llvm/test/Transforms/InstCombine/ctpop.ll
index e8e3603..33b95b0 100644
--- a/llvm/test/Transforms/InstCombine/ctpop.ll
+++ b/llvm/test/Transforms/InstCombine/ctpop.ll
@@ -46,7 +46,7 @@ define i1 @test3(i32 %arg) {
 ; Negative test for when we know nothing
 define i1 @test4(i8 %arg) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[ARG:%.*]]), !range ![[RANGE:[0-9]+]]
+; CHECK-NEXT:    [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[ARG:%.*]]), !range ![[$RANGE:[0-9]+]]
 ; CHECK-NEXT:    [[RES:%.*]] = icmp eq i8 [[CNT]], 2
 ; CHECK-NEXT:    ret i1 [[RES]]
 ;
@@ -94,4 +94,4 @@ define i1 @test6(i1 %arg) {
   ret i1 %cnt
 }
 
-; CHECK: ![[RANGE]] = !{i8 0, i8 9}
+; CHECK: ![[$RANGE]] = !{i8 0, i8 9}
diff --git a/llvm/test/Transforms/InstCombine/err-rep-cold.ll b/llvm/test/Transforms/InstCombine/err-rep-cold.ll
index 6c4e4e1..763a575 100644
--- a/llvm/test/Transforms/InstCombine/err-rep-cold.ll
+++ b/llvm/test/Transforms/InstCombine/err-rep-cold.ll
@@ -1,5 +1,5 @@
 ; Test the static branch probability heuristics for error-reporting functions.
-; RUN: opt < %s -instcombine -S | FileCheck %s
+; RUN: opt < %s -instcombine -S | FileCheck -enable-var-scope %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
@@ -22,7 +22,7 @@ if.then:                                          ; preds = %entry
   %call = tail call i32 (%struct._IO_FILE*, i8*, ...) @fprintf(%struct._IO_FILE* %0, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i64 0, i64 0), i32 %a) #1
   br label %return
 
-; CHECK: %call = tail call i32 (%struct._IO_FILE*, i8*, ...) @fprintf(%struct._IO_FILE* %0, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i64 0, i64 0), i32 %a) #[[AT1:[0-9]+]]
+; CHECK: %call = tail call i32 (%struct._IO_FILE*, i8*, ...) @fprintf(%struct._IO_FILE* %0, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i64 0, i64 0), i32 %a) #[[$AT1:[0-9]+]]
 
 return:                                           ; preds = %entry, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
@@ -42,7 +42,7 @@ if.then:                                          ; preds = %entry
   %1 = tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0)
   br label %return
 
-; CHECK: tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0) #[[AT2:[0-9]+]]
+; CHECK: tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0) #[[$AT2:[0-9]+]]
 
 return:                                           ; preds = %entry, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
@@ -62,7 +62,7 @@ if.then:                                          ; preds = %entry
   %1 = tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0)
   br label %return
 
-; CHECK-NOT: tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0) #[[AT2]]
+; CHECK-NOT: tail call i64 @fwrite(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str1, i64 0, i64 0), i64 8, i64 1, %struct._IO_FILE* %0) #[[$AT2]]
 
 return:                                           ; preds = %entry, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
@@ -72,6 +72,6 @@ return:                                           ; preds = %entry, %if.then
 attributes #0 = { nounwind uwtable }
 attributes #1 = { nounwind }
 
-; CHECK: attributes #[[AT1]] = { cold nounwind }
-; CHECK: attributes #[[AT2]] = { cold }
+; CHECK: attributes #[[$AT1]] = { cold nounwind }
+; CHECK: attributes #[[$AT2]] = { cold }
 
diff --git a/llvm/test/Transforms/InstCombine/getelementptr.ll b/llvm/test/Transforms/InstCombine/getelementptr.ll
index de8190d..ebd5f57 100644
--- a/llvm/test/Transforms/InstCombine/getelementptr.ll
+++ b/llvm/test/Transforms/InstCombine/getelementptr.ll
@@ -622,7 +622,7 @@ define i32 @test35() nounwind {
              i8* getelementptr (%t1, %t1* bitcast (%t0* @s to %t1*), i32 0, i32 1, i32 0)) nounwind
   ret i32 0
 ; CHECK-LABEL: @test35(
-; CHECK: call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @"\01LC8", i64 0, i64 0), i8* getelementptr inbounds (%t0, %t0* @s, i64 0, i32 1, i64 0)) [[NUW:#[0-9]+]]
+; CHECK: call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @"\01LC8", i64 0, i64 0), i8* getelementptr inbounds (%t0, %t0* @s, i64 0, i32 1, i64 0)) [[$NUW:#[0-9]+]]
 }
 
 ; Don't treat signed offsets as unsigned.
@@ -942,4 +942,4 @@ define <2 x i32*> @PR32414(i32** %ptr) {
   ret <2 x i32*> %tmp1
 }
 
-; CHECK: attributes [[NUW]] = { nounwind }
+; CHECK: attributes [[$NUW]] = { nounwind }
diff --git a/llvm/test/Transforms/InstCombine/intrinsics.ll b/llvm/test/Transforms/InstCombine/intrinsics.ll
index 8d2f06e..c6f88fb 100644
--- a/llvm/test/Transforms/InstCombine/intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/intrinsics.ll
@@ -328,7 +328,7 @@ define <2 x i1> @cttz_knownbits_vec(<2 x i32> %arg) {
 define i1 @cttz_knownbits2(i32 %arg) {
 ; CHECK-LABEL: @cttz_knownbits2(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[ARG:%.*]], 4
-; CHECK-NEXT:    [[CNT:%.*]] = call i32 @llvm.cttz.i32(i32 [[OR]], i1 true) #2, !range ![[CTTZ_RANGE:[0-9]+]]
+; CHECK-NEXT:    [[CNT:%.*]] = call i32 @llvm.cttz.i32(i32 [[OR]], i1 true) #2, !range ![[$CTTZ_RANGE:[0-9]+]]
 ; CHECK-NEXT:    [[RES:%.*]] = icmp eq i32 [[CNT]], 2
 ; CHECK-NEXT:    ret i1 [[RES]]
 ;
@@ -428,7 +428,7 @@ define <2 x i1> @ctlz_knownbits_vec(<2 x i8> %arg) {
 define i1 @ctlz_knownbits2(i8 %arg) {
 ; CHECK-LABEL: @ctlz_knownbits2(
 ; CHECK-NEXT:    [[OR:%.*]] = or i8 [[ARG:%.*]], 32
-; CHECK-NEXT:    [[CNT:%.*]] = call i8 @llvm.ctlz.i8(i8 [[OR]], i1 true) #2, !range ![[CTLZ_RANGE:[0-9]+]]
+; CHECK-NEXT:    [[CNT:%.*]] = call i8 @llvm.ctlz.i8(i8 [[OR]], i1 true) #2, !range ![[$CTLZ_RANGE:[0-9]+]]
 ; CHECK-NEXT:    [[RES:%.*]] = icmp eq i8 [[CNT]], 2
 ; CHECK-NEXT:    ret i1 [[RES]]
 ;
@@ -745,5 +745,5 @@ define void @nearbyint(double *%P) {
   ret void
 }
 
-; CHECK: [[CTTZ_RANGE]] = !{i32 0, i32 3}
-; CHECK: [[CTLZ_RANGE]] = !{i8 0, i8 3}
+; CHECK: [[$CTTZ_RANGE]] = !{i32 0, i32 3}
+; CHECK: [[$CTLZ_RANGE]] = !{i8 0, i8 3}
diff --git a/llvm/test/Transforms/InstCombine/phi-select-constant.ll b/llvm/test/Transforms/InstCombine/phi-select-constant.ll
index 83c4efb..2b0bf43 100644
--- a/llvm/test/Transforms/InstCombine/phi-select-constant.ll
+++ b/llvm/test/Transforms/InstCombine/phi-select-constant.ll
@@ -61,22 +61,22 @@ final:
 ; phi has constant vectors along with a single non-constant vector as operands.
 define <2 x i8> @vec3(i1 %cond1, i1 %cond2, <2 x i1> %x, <2 x i8> %y, <2 x i8> %z) {
 ; CHECK-LABEL: @vec3
-; CHECK-LABEL: entry:
+; CHECK: entry:
 ; CHECK-NEXT: [[PHITMP1:%.*]] = shufflevector <2 x i8> %y, <2 x i8> %z, <2 x i32> <i32 2, i32 1>
 entry:
   br i1 %cond1, label %if1, label %else
 
-; CHECK-LABEL: if1:
+; CHECK: if1:
 ; CHECK-NEXT: [[PHITMP2:%.*]] = shufflevector <2 x i8> %y, <2 x i8> %z, <2 x i32> <i32 0, i32 3>
 if1:
   br i1 %cond2, label %if2, label %else
 
-; CHECK-LABEL: if2:
+; CHECK: if2:
 ; CHECK-NEXT: [[PHITMP3:%.*]] = select <2 x i1> %x, <2 x i8> %y, <2 x i8> %z
 if2:
   br label %else
 
-; CHECK-LABEL: else:
+; CHECK: else:
 ; CHECK-NEXT: [[PHITMP4:%.*]] = phi <2 x i8> [ [[PHITMP3]], %if2 ], [ [[PHITMP1]], %entry ], [ [[PHITMP2]], %if1 ]
 ; CHECK-NEXT: ret <2 x i8> [[PHITMP4]]
 else:
diff --git a/llvm/test/Transforms/InstCombine/pow-1.ll b/llvm/test/Transforms/InstCombine/pow-1.ll
index 602c20a..6fcb92a 100644
--- a/llvm/test/Transforms/InstCombine/pow-1.ll
+++ b/llvm/test/Transforms/InstCombine/pow-1.ll
@@ -71,7 +71,7 @@ define double @test_simplify6(double %x) {
 define float @test_simplify7(float %x) {
 ; CHECK-LABEL: @test_simplify7(
   %retval = call float @powf(float %x, float 0.5)
-; CHECK-NEXT: [[SQRTF:%[a-z0-9]+]] = call float @sqrtf(float %x) [[NUW_RO:#[0-9]+]]
+; CHECK-NEXT: [[SQRTF:%[a-z0-9]+]] = call float @sqrtf(float %x) [[$NUW_RO:#[0-9]+]]
 ; CHECK-NEXT: [[FABSF:%[a-z0-9]+]] = call float @llvm.fabs.f32(float [[SQRTF]])
 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq float %x, 0xFFF0000000000000
 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], float 0x7FF0000000000000, float [[FABSF]]
@@ -82,7 +82,7 @@ define float @test_simplify7(float %x) {
 define double @test_simplify8(double %x) {
 ; CHECK-LABEL: @test_simplify8(
   %retval = call double @pow(double %x, double 0.5)
-; CHECK-NEXT: [[SQRT:%[a-z0-9]+]] = call double @sqrt(double %x) [[NUW_RO]]
+; CHECK-NEXT: [[SQRT:%[a-z0-9]+]] = call double @sqrt(double %x) [[$NUW_RO]]
 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @llvm.fabs.f64(double [[SQRT]])
 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq double %x, 0xFFF0000000000000
 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
@@ -175,7 +175,7 @@ define double @test_simplify17(double %x) {
 define float @test_simplify18(float %x) {
 ; CHECK-LABEL: @test_simplify18(
   %retval = call float @powf(float 10.0, float %x)
-; CHECK-EXP10: [[EXP10F:%[_a-z0-9]+]] = call float @__exp10f(float %x) [[NUW_RO:#[0-9]+]]
+; CHECK-EXP10: [[EXP10F:%[_a-z0-9]+]] = call float @__exp10f(float %x) [[$NUW_RO:#[0-9]+]]
   ret float %retval
 ; CHECK-EXP10: ret float [[EXP10F]]
 ; CHECK-NO-EXP10: call float @powf
@@ -184,11 +184,11 @@ define float @test_simplify18(float %x) {
 define double @test_simplify19(double %x) {
 ; CHECK-LABEL: @test_simplify19(
   %retval = call double @pow(double 10.0, double %x)
-; CHECK-EXP10: [[EXP10:%[_a-z0-9]+]] = call double @__exp10(double %x) [[NUW_RO]]
+; CHECK-EXP10: [[EXP10:%[_a-z0-9]+]] = call double @__exp10(double %x) [[$NUW_RO]]
   ret double %retval
 ; CHECK-EXP10: ret double [[EXP10]]
 ; CHECK-NO-EXP10: call double @pow
 }
 
-; CHECK: attributes [[NUW_RO]] = { nounwind readonly }
+; CHECK: attributes [[$NUW_RO]] = { nounwind readonly }
 
diff --git a/llvm/test/Transforms/InstCombine/printf-1.ll b/llvm/test/Transforms/InstCombine/printf-1.ll
index 2a513d0..ce1a91d 100644
--- a/llvm/test/Transforms/InstCombine/printf-1.ll
+++ b/llvm/test/Transforms/InstCombine/printf-1.ll
@@ -14,7 +14,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 @percent_f = constant [3 x i8] c"%f\00"
 @percent_s = constant [4 x i8] c"%s\0A\00"
 @empty = constant [1 x i8] c"\00"
-; CHECK: [[STR:@[a-z0-9]+]] = private unnamed_addr constant [12 x i8] c"hello world\00"
+; CHECK: [[$STR:@[a-z0-9]+]] = private unnamed_addr constant [12 x i8] c"hello world\00"
 
 declare i32 @printf(i8*, ...)
 
@@ -65,7 +65,7 @@ define void @test_simplify4() {
 ; CHECK-LABEL: @test_simplify4(
   %fmt = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0
   call i32 (i8*, ...) @printf(i8* %fmt)
-; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* [[STR]], i32 0, i32 0))
+; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* [[$STR]], i32 0, i32 0))
   ret void
 ; CHECK-NEXT: ret void
 }
diff --git a/llvm/test/Transforms/InstCombine/rem.ll b/llvm/test/Transforms/InstCombine/rem.ll
index 86a3580..4e90b33 100644
--- a/llvm/test/Transforms/InstCombine/rem.ll
+++ b/llvm/test/Transforms/InstCombine/rem.ll
@@ -441,7 +441,7 @@ define i32 @pr27968_0(i1 %c0, i32* %p) {
 ; CHECK-NEXT:    br label %if.end
 ; CHECK:       if.end:
 ; CHECK-NEXT:    [[LHS:%.*]] = phi i32 [ [[V]], %if.then ], [ 5, %entry ]
-; CHECK-NEXT:    br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label [[REM]].is.safe, label [[REM]].is.unsafe
+; CHECK-NEXT:    br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label %rem.is.safe, label %rem.is.unsafe
 ; CHECK:       rem.is.safe:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 [[LHS]], zext (i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b) to i32)
 ; CHECK-NEXT:    ret i32 [[REM]]
@@ -476,7 +476,7 @@ define i32 @pr27968_1(i1 %c0, i1 %always_false, i32* %p) {
 ; CHECK-NEXT:    br label %if.end
 ; CHECK:       if.end:
 ; CHECK-NEXT:    [[LHS:%.*]] = phi i32 [ [[V]], %if.then ], [ 5, %entry ]
-; CHECK-NEXT:    br i1 %always_false, label [[REM]].is.safe, label [[REM]].is.unsafe
+; CHECK-NEXT:    br i1 %always_false, label %rem.is.safe, label %rem.is.unsafe
 ; CHECK:       rem.is.safe:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 [[LHS]], -2147483648
 ; CHECK-NEXT:    ret i32 [[REM]]
@@ -511,7 +511,7 @@ define i32 @pr27968_2(i1 %c0, i32* %p) {
 ; CHECK-NEXT:    br label %if.end
 ; CHECK:       if.end:
 ; CHECK-NEXT:    [[LHS:%.*]] = phi i32 [ [[V]], %if.then ], [ 5, %entry ]
-; CHECK-NEXT:    br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label [[REM]].is.safe, label [[REM]].is.unsafe
+; CHECK-NEXT:    br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label %rem.is.safe, label %rem.is.unsafe
 ; CHECK:       rem.is.safe:
 ; CHECK-NEXT:    [[REM:%.*]] = urem i32 [[LHS]], zext (i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b) to i32)
 ; CHECK-NEXT:    ret i32 [[REM]]
diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index 1bf9c99..e49639b 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -1240,7 +1240,7 @@ define i8* @test83(i1 %flag) {
 ; CHECK:         %[[V:.*]] = load i64, i64* %[[X2]]
 ; CHECK-NEXT:    store i64 %[[V]], i64* %[[Y2]]
 ; CHECK-NEXT:    %[[C:.*]] = inttoptr i64 %[[V]] to i8*
-; CHECK-NEXT:    ret i8* %[[S]]
+; CHECK-NEXT:    ret i8* %[[C]]
 entry:
   %x = alloca i8*
   %y = alloca i64
diff --git a/llvm/test/Transforms/InstCombine/select_meta.ll b/llvm/test/Transforms/InstCombine/select_meta.ll
index 7d5771a..5a146de 100644
--- a/llvm/test/Transforms/InstCombine/select_meta.ll
+++ b/llvm/test/Transforms/InstCombine/select_meta.ll
@@ -6,7 +6,7 @@
 define i32 @foo(i32) local_unnamed_addr #0  {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 %0, 2
-; CHECK-NEXT:    [[DOTV:%.*]] = select i1 [[TMP2]], i32 20, i32 -20, !prof ![[MD1:[0-9]+]]
+; CHECK-NEXT:    [[DOTV:%.*]] = select i1 [[TMP2]], i32 20, i32 -20, !prof ![[$MD1:[0-9]+]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[DOTV]], %0
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -20,7 +20,7 @@ define i32 @foo(i32) local_unnamed_addr #0  {
 define i8 @shrink_select(i1 %cond, i32 %x) {
 ; CHECK-LABEL: @shrink_select(
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 %x to i8
-; CHECK-NEXT:    [[TRUNC:%.*]] = select i1 %cond, i8 [[TMP1]], i8 42, !prof ![[MD1]]
+; CHECK-NEXT:    [[TRUNC:%.*]] = select i1 %cond, i8 [[TMP1]], i8 42, !prof ![[$MD1]]
 ; CHECK-NEXT:    ret i8 [[TRUNC]]
 ;
   %sel = select i1 %cond, i32 %x, i32 42, !prof !1
@@ -31,8 +31,8 @@ define i8 @shrink_select(i1 %cond, i32 %x) {
 define void @min_max_bitcast(<4 x float> %a, <4 x float> %b, <4 x i32>* %ptr1, <4 x i32>* %ptr2) {
 ; CHECK-LABEL: @min_max_bitcast(
 ; CHECK-NEXT:    [[CMP:%.*]] = fcmp olt <4 x float> %a, %b
-; CHECK-NEXT:    [[SEL1_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> %a, <4 x float> %b, !prof ![[MD1]]
-; CHECK-NEXT:    [[SEL2_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> %b, <4 x float> %a, !prof ![[MD1]]
+; CHECK-NEXT:    [[SEL1_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> %a, <4 x float> %b, !prof ![[$MD1]]
+; CHECK-NEXT:    [[SEL2_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> %b, <4 x float> %a, !prof ![[$MD1]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32>* %ptr1 to <4 x float>*
 ; CHECK-NEXT:    store <4 x float> [[SEL1_V]], <4 x float>* [[TMP1]], align 16
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x i32>* %ptr2 to <4 x float>*
@@ -53,7 +53,7 @@ define i32 @foo2(i32, i32) local_unnamed_addr #0  {
 ; CHECK-LABEL: @foo2(
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp sgt i32 %0, 2
 ; CHECK-NEXT:    [[TMP4:%.*]] = sub i32 0, %1
-; CHECK-NEXT:    [[DOTP:%.*]] = select i1 [[TMP3]], i32 %1, i32 [[TMP4]], !prof ![[MD1]]
+; CHECK-NEXT:    [[DOTP:%.*]] = select i1 [[TMP3]], i32 %1, i32 [[TMP4]], !prof ![[$MD1]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[DOTP]], %0
 ; CHECK-NEXT:    ret i32 [[TMP5]]
 ;
@@ -68,7 +68,7 @@ define i64 @test43(i32 %a) nounwind {
 ; CHECK-LABEL: @test43(
 ; CHECK-NEXT:    [[A_EXT:%.*]] = sext i32 %a to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i64 [[A_EXT]], 0
-; CHECK-NEXT:    [[MAX:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 0, !prof ![[MD1]]
+; CHECK-NEXT:    [[MAX:%.*]] = select i1 [[TMP1]], i64 [[A_EXT]], i64 0, !prof ![[$MD1]]
 ; CHECK-NEXT:    ret i64 [[MAX]]
 ;
   %a_ext = sext i32 %a to i64
@@ -79,7 +79,7 @@ define i64 @test43(i32 %a) nounwind {
 
 define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) {
 ; CHECK-LABEL: @scalar_select_of_vectors_sext(
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 %ccb, <2 x i1> %cca, <2 x i1> zeroinitializer, !prof ![[MD1]]
+; CHECK-NEXT:    [[NARROW:%.*]] = select i1 %ccb, <2 x i1> %cca, <2 x i1> zeroinitializer, !prof ![[$MD1]]
 ; CHECK-NEXT:    [[R:%.*]] = sext <2 x i1> [[NARROW]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -92,7 +92,7 @@ define <2 x i32> @scalar_select_of_vectors_sext(<2 x i1> %cca, i1 %ccb) {
 define i16 @t7(i32 %a) {
 ; CHECK-LABEL: @t7(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 %a, -32768
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 %a, i32 -32768, !prof ![[MD1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 %a, i32 -32768, !prof ![[$MD1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
 ; CHECK-NEXT:    ret i16 [[TMP3]]
 ;
@@ -106,7 +106,7 @@ define i32 @abs_nabs_x01(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x01(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 %x, -1
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, %x
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 %x, i32 [[SUB]], !prof ![[MD1]]
+; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 %x, i32 [[SUB]], !prof ![[$MD1]]
 ; CHECK-NEXT:    ret i32 [[COND1]]
 ;
   %cmp = icmp sgt i32 %x, -1
@@ -122,7 +122,7 @@ define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @abs_nabs_x01_vec(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, %x
-; CHECK-NEXT:    [[COND1:%.*]] = select <2 x i1> [[CMP]], <2 x i32> %x, <2 x i32> [[SUB]], !prof ![[MD1]]
+; CHECK-NEXT:    [[COND1:%.*]] = select <2 x i1> [[CMP]], <2 x i32> %x, <2 x i32> [[SUB]], !prof ![[$MD1]]
 ; CHECK-NEXT:    ret <2 x i32> [[COND1]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
@@ -138,7 +138,7 @@ define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
 define i32 @test30(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test30(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 %x, %y
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 %x, i32 %y, !prof ![[MD1]]
+; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 %x, i32 %y, !prof ![[$MD1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, %y
@@ -153,7 +153,7 @@ define i32 @test30(i32 %x, i32 %y) {
 define i32 @test70(i32 %x) {
 ; CHECK-LABEL: @test70(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 %x, 75
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[TMP1]], i32 %x, i32 75, !prof ![[MD3:[0-9]+]]
+; CHECK-NEXT:    [[COND:%.*]] = select i1 [[TMP1]], i32 %x, i32 75, !prof ![[$MD3:[0-9]+]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 75
@@ -168,7 +168,7 @@ define i32 @test70(i32 %x) {
 define i32 @test72(i32 %x) {
 ; CHECK-LABEL: @test72(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 %x, 11
-; CHECK-NEXT:    [[RETVAL:%.*]] = select i1 [[TMP1]], i32 %x, i32 11, !prof ![[MD4:[0-9]+]]
+; CHECK-NEXT:    [[RETVAL:%.*]] = select i1 [[TMP1]], i32 %x, i32 11, !prof ![[$MD4:[0-9]+]]
 ; CHECK-NEXT:    ret i32 [[RETVAL]]
 ;
   %cmp = icmp sgt i32 %x, 92
@@ -183,7 +183,7 @@ define i32 @test72(i32 %x) {
 define i32 @test74(i32 %x) {
 ; CHECK-LABEL: @test74(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 %x, 75
-; CHECK-NEXT:    [[RETVAL:%.*]] = select i1 [[TMP1]], i32 %x, i32 75, !prof ![[MD4]]
+; CHECK-NEXT:    [[RETVAL:%.*]] = select i1 [[TMP1]], i32 %x, i32 75, !prof ![[$MD4]]
 ; CHECK-NEXT:    ret i32 [[RETVAL]]
 ;
   %cmp = icmp slt i32 %x, 36
@@ -198,7 +198,7 @@ define i32 @smin1(i32 %x) {
 ; CHECK-LABEL: @smin1(
 ; CHECK-NEXT:    [[NOT_X:%.*]] = xor i32 %x, -1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[NOT_X]], -1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[NOT_X]], i32 -1, !prof ![[MD1]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[NOT_X]], i32 -1, !prof ![[$MD1]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %not_x = xor i32 %x, -1
@@ -212,7 +212,7 @@ define i32 @smin2(i32 %x) {
 ; CHECK-LABEL: @smin2(
 ; CHECK-NEXT:    [[NOT_X:%.*]] = xor i32 %x, -1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[NOT_X]], -1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[NOT_X]], i32 -1, !prof ![[MD3]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[NOT_X]], i32 -1, !prof ![[$MD3]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %not_x = xor i32 %x, -1
@@ -226,7 +226,7 @@ define i32 @smax1(i32 %x) {
 ; CHECK-LABEL: @smax1(
 ; CHECK-NEXT:    [[NOT_X:%.*]] = xor i32 %x, -1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[NOT_X]], -1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[NOT_X]], i32 -1, !prof ![[MD1]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[NOT_X]], i32 -1, !prof ![[$MD1]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %not_x = xor i32 %x, -1
@@ -240,7 +240,7 @@ define i32 @smax2(i32 %x) {
 ; CHECK-LABEL: @smax2(
 ; CHECK-NEXT:    [[NOT_X:%.*]] = xor i32 %x, -1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[NOT_X]], -1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[NOT_X]], i32 -1, !prof ![[MD3]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[NOT_X]], i32 -1, !prof ![[$MD3]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %not_x = xor i32 %x, -1
@@ -253,7 +253,7 @@ define i32 @smax2(i32 %x) {
 define i32 @umin1(i32 %x) {
 ; CHECK-LABEL: @umin1(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 %x, -2147483648
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 -2147483648, !prof ![[MD1]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 -2147483648, !prof ![[$MD1]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %cmp = icmp sgt i32 %x, -1
@@ -265,7 +265,7 @@ define i32 @umin1(i32 %x) {
 define i32 @umin2(i32 %x) {
 ; CHECK-LABEL: @umin2(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 %x, 2147483647
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 2147483647, !prof ![[MD3]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 2147483647, !prof ![[$MD3]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %cmp = icmp slt i32 %x, 0
@@ -277,7 +277,7 @@ define i32 @umin2(i32 %x) {
 define i32 @umax1(i32 %x) {
 ; CHECK-LABEL: @umax1(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 %x, 2147483647
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 2147483647, !prof ![[MD1]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 2147483647, !prof ![[$MD1]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %cmp = icmp slt i32 %x, 0
@@ -289,7 +289,7 @@ define i32 @umax1(i32 %x) {
 define i32 @umax2(i32 %x) {
 ; CHECK-LABEL: @umax2(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i32 %x, -2147483648
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 -2147483648, !prof ![[MD3]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 -2147483648, !prof ![[$MD3]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
   %cmp = icmp sgt i32 %x, -1
@@ -300,7 +300,7 @@ define i32 @umax2(i32 %x) {
 !1 = !{!"branch_weights", i32 2, i32 10}
 !2 = !{!"branch_weights", i32 3, i32 10}
 
-; CHECK-DAG: ![[MD1]] = !{!"branch_weights", i32 2, i32 10}
-; CHECK-DAG: ![[MD3]] = !{!"branch_weights", i32 10, i32 2}
-; CHECK-DAG: ![[MD4]] = !{!"branch_weights", i32 10, i32 3}
+; CHECK-DAG: ![[$MD1]] = !{!"branch_weights", i32 2, i32 10}
+; CHECK-DAG: ![[$MD3]] = !{!"branch_weights", i32 10, i32 2}
+; CHECK-DAG: ![[$MD4]] = !{!"branch_weights", i32 10, i32 3}
 
diff --git a/llvm/test/Transforms/JumpThreading/basic.ll b/llvm/test/Transforms/JumpThreading/basic.ll
index 14cd1fb..ce86cba 100644
--- a/llvm/test/Transforms/JumpThreading/basic.ll
+++ b/llvm/test/Transforms/JumpThreading/basic.ll
@@ -89,7 +89,7 @@ T1:
 F1:
 	%v2 = call i32 @f2()
 ; CHECK:   %v2 = call i32 @f2()
-; CHECK-NEXT:   br i1 %cond2, 
+; CHECK-NEXT:   br i1 %cond2,
 	br label %Merge
 
 Merge:
@@ -156,11 +156,11 @@ define i32 @test6(i32 %A) {
 ; CHECK: call void @f3()
 ; CHECK-NOT: br
 ; CHECK: ret i32 4
-    
+
 BB2:
 	call i32 @f1()
 	br label %BB1
-        
+
 
 BB1:
 	%tmp459 = icmp eq i32 %A, 42
@@ -217,7 +217,7 @@ define i32 @test8b(i1 %cond, i1 %cond2) {
 T0:
         %A = call i1 @test8a()
 	br i1 %A, label %T1, label %F1
-        
+
 ; CHECK: T0:
 ; CHECK-NEXT: call
 ; CHECK-NEXT: br i1 %A, label %T1, label %Y
@@ -305,7 +305,7 @@ define i32 @test10g(i1 %cond) {
 T1:
         %v1 = call i32 @test10f1()
         br label %Merge
-        
+
 ; CHECK: %v1 = call i32 @test10f1()
 ; CHECK-NEXT: call void @f3()
 ; CHECK-NEXT: ret i32 %v1
@@ -334,13 +334,13 @@ define i32 @test11(i32 %A) {
 ; CHECK-NEXT: br i1 %tmp455, label %BB4, label %BB2
 	%tmp455 = icmp eq i32 %A, 42
 	br i1 %tmp455, label %BB1, label %BB2
-        
+
 BB2:
 ; CHECK: call i32 @f1()
 ; CHECK-NEXT: ret i32 %C
 	%C = call i32 @f1()
 	ret i32 %C
-        
+
 
 BB1:
 	%tmp459 = icmp eq i32 %A, 43
@@ -366,7 +366,7 @@ entry:
 ; CHECK-NEXT: %cond = icmp eq i32 %A, 0
 ; CHECK-NEXT: br i1 %cond, label %bb1, label %return
 
-bb:                   
+bb:
   %B = call i32 @test10f2()
   br label %bb1
 
@@ -412,7 +412,7 @@ T2:
 
 F2:
 	ret i32 %v1
-        
+
 ; CHECK:   br i1 %cond, label %F2, label %Merge
 
 ; CHECK:      Merge:
@@ -491,9 +491,9 @@ F1:
 
 Merge:
 	%B = phi i32 [0, %Entry], [%v1, %F1]
-	%M = icmp eq i32 %B, 0 
+	%M = icmp eq i32 %B, 0
 	%M1 = zext i1 %M to i32
-	%N = icmp eq i32 %M1, 0 
+	%N = icmp eq i32 %M1, 0
 	br i1 %N, label %T2, label %F2
 
 ; CHECK: Merge:
@@ -501,7 +501,7 @@ Merge:
 ; CHECK-NEXT:   %v1 = call i32 @f1()
 
 T2:
-	%Q = call i32 @f2() 
+	%Q = call i32 @f2()
 	ret i32 %Q
 
 F2:
@@ -531,8 +531,8 @@ l2:
   br label %l3
 
 l3:
-; CHECK: call void @g() [[NOD:#[0-9]+]]
-; CHECK-NOT: call void @g() [[NOD]]
+; CHECK: call void @g() [[$NOD:#[0-9]+]]
+; CHECK-NOT: call void @g() [[$NOD]]
   call void @g() noduplicate
   %y = icmp ult i32 %p, 5
   br i1 %y, label %l4, label %l5
@@ -561,8 +561,8 @@ l2:
   br label %l3
 
 l3:
-; CHECK: call void @g() [[CON:#[0-9]+]]
-; CHECK-NOT: call void @g() [[CON]]
+; CHECK: call void @g() [[$CON:#[0-9]+]]
+; CHECK-NOT: call void @g() [[$CON]]
   call void @g() convergent
   %y = icmp ult i32 %p, 5
   br i1 %y, label %l4, label %l5
@@ -578,5 +578,5 @@ l5:
 }
 
 
-; CHECK: attributes [[NOD]] = { noduplicate }
-; CHECK: attributes [[CON]] = { convergent }
+; CHECK: attributes [[$NOD]] = { noduplicate }
+; CHECK: attributes [[$CON]] = { convergent }
diff --git a/llvm/test/Transforms/MemCpyOpt/memcpy.ll b/llvm/test/Transforms/MemCpyOpt/memcpy.ll
index e4d50f7..9f0ad2d 100644
--- a/llvm/test/Transforms/MemCpyOpt/memcpy.ll
+++ b/llvm/test/Transforms/MemCpyOpt/memcpy.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -basicaa -memcpyopt -dse -S | FileCheck %s
+; RUN: opt < %s -basicaa -memcpyopt -dse -S | FileCheck -enable-var-scope %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i686-apple-darwin9"
@@ -29,7 +29,7 @@ entry:
 ; CHECK: ret void
 }
 
-declare void @ccoshl(%0* nocapture sret, x86_fp80, x86_fp80) nounwind 
+declare void @ccoshl(%0* nocapture sret, x86_fp80, x86_fp80) nounwind
 
 
 ; The intermediate alloca and one of the memcpy's should be eliminated, the
@@ -40,7 +40,7 @@ define void @test2(i8* %P, i8* %Q) nounwind  {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %R, i8* %P, i32 32, i32 16, i1 false)
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %Q, i8* %R, i32 32, i32 16, i1 false)
   ret void
-        
+
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT: call void @llvm.memmove{{.*}}(i8* %Q, i8* %P
 ; CHECK-NEXT: ret void
@@ -59,7 +59,7 @@ define void @test3(%0* noalias sret %agg.result) nounwind  {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %agg.result2, i8* %x.01, i32 32, i32 16, i1 false)
   ret void
 ; CHECK-LABEL: @test3(
-; CHECK-NEXT: %agg.result1 = bitcast 
+; CHECK-NEXT: %agg.result1 = bitcast
 ; CHECK-NEXT: call void @llvm.memcpy
 ; CHECK-NEXT: ret void
 }
@@ -137,7 +137,7 @@ entry:
   %call = call i32 @g(%struct.p* align 8 byval %agg.tmp) nounwind
   ret i32 %call
 ; CHECK-LABEL: @test7(
-; CHECK: call i32 @g(%struct.p* byval align 8 %q) [[NUW:#[0-9]+]]
+; CHECK: call i32 @g(%struct.p* byval align 8 %q) [[$NUW:#[0-9]+]]
 }
 
 declare i32 @g(%struct.p* align 8 byval)
@@ -233,7 +233,7 @@ declare void @llvm.memcpy.p1i8.p0i8.i64(i8 addrspace(1)* nocapture, i8* nocaptur
 declare void @f1(%struct.big* nocapture sret)
 declare void @f2(%struct.big*)
 
-; CHECK: attributes [[NUW]] = { nounwind }
+; CHECK: attributes [[$NUW]] = { nounwind }
 ; CHECK: attributes #1 = { argmemonly nounwind }
 ; CHECK: attributes #2 = { nounwind ssp }
 ; CHECK: attributes #3 = { nounwind ssp uwtable }
diff --git a/llvm/test/Transforms/SimplifyCFG/PowerPC/cttz-ctlz-spec.ll b/llvm/test/Transforms/SimplifyCFG/PowerPC/cttz-ctlz-spec.ll
index fa74549..29da286 100644
--- a/llvm/test/Transforms/SimplifyCFG/PowerPC/cttz-ctlz-spec.ll
+++ b/llvm/test/Transforms/SimplifyCFG/PowerPC/cttz-ctlz-spec.ll
@@ -1,4 +1,4 @@
-; RUN: opt -S -simplifycfg < %s | FileCheck %s
+; RUN: opt -S -simplifycfg < %s | FileCheck -enable-var-scope %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -25,7 +25,7 @@ define i64 @test1b(i64 %A) {
 ; CHECK-LABEL: @test1b(
 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
-; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
+; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
 ; CHECK-NEXT: ret i64 [[SEL]]
 entry:
   %tobool = icmp eq i64 %A, 0
diff --git a/llvm/test/Transforms/SimplifyCFG/inline-asm-sink.ll b/llvm/test/Transforms/SimplifyCFG/inline-asm-sink.ll
index 9dd04a2..da281d6 100644
--- a/llvm/test/Transforms/SimplifyCFG/inline-asm-sink.ll
+++ b/llvm/test/Transforms/SimplifyCFG/inline-asm-sink.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -mem2reg -simplifycfg -S | FileCheck %s
+; RUN: opt < %s -mem2reg -simplifycfg -S | FileCheck -enable-var-scope %s
 
 define i32 @test(i32 %x) {
 ; CHECK-LABEL: @test
@@ -8,21 +8,21 @@ entry:
   br i1 %tobool, label %if.then, label %if.else
 
 if.then:
-; CHECK-LABEL: if.then:
+; CHECK: if.then:
 ; CHECK: [[ASM1:%.*]] = call i32 asm "mov $0, #1", "=r"()
   %tmp1 = call i32 asm "mov $0, #1", "=r"() nounwind readnone
   store i32 %tmp1, i32* %y, align 4
   br label %if.end
 
 if.else:
-; CHECK-LABEL: if.else:
+; CHECK: if.else:
 ; CHECK: [[ASM2:%.*]] = call i32 asm "mov $0, #2", "=r"()
   %tmp2 = call i32 asm "mov $0, #2", "=r"() nounwind readnone
   store i32 %tmp2, i32* %y, align 4
   br label %if.end
 
 if.end:
-; CHECK-LABEL: if.end:
+; CHECK: if.end:
 ; CHECK: {{%.*}} = phi i32 [ [[ASM1]], %if.then ], [ [[ASM2]], %if.else ]
   %tmp3 = load i32, i32* %y, align 4
   ret i32 %tmp3
diff --git a/llvm/test/Transforms/SimplifyCFG/sink-common-code.ll b/llvm/test/Transforms/SimplifyCFG/sink-common-code.ll
index c5f4639..a261453 100644
--- a/llvm/test/Transforms/SimplifyCFG/sink-common-code.ll
+++ b/llvm/test/Transforms/SimplifyCFG/sink-common-code.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -simplifycfg -S | FileCheck %s
+; RUN: opt < %s -simplifycfg -S | FileCheck -enable-var-scope %s
 
 define zeroext i1 @test1(i1 zeroext %flag, i32 %blksA, i32 %blksB, i32 %nblks) {
 entry:
@@ -340,7 +340,7 @@ if.end:
 ; CHECK-LABEL: test13
 ; CHECK-DAG: select
 ; CHECK-DAG: load volatile
-; CHECK: store volatile {{.*}}, !tbaa ![[TBAA:[0-9]]]
+; CHECK: store volatile {{.*}}, !tbaa ![[$TBAA:[0-9]]]
 ; CHECK-NOT: load
 ; CHECK-NOT: store
 
@@ -842,6 +842,6 @@ if.end:
 ; CHECK: insertvalue
 ; CHECK-NOT: insertvalue
 
-; CHECK: ![[TBAA]] = !{![[TYPE:[0-9]]], ![[TYPE]], i64 0}
+; CHECK: ![[$TBAA]] = !{![[TYPE:[0-9]]], ![[TYPE]], i64 0}
 ; CHECK: ![[TYPE]] = !{!"float", ![[TEXT:[0-9]]]}
 ; CHECK: ![[TEXT]] = !{!"an example type tree"}
diff --git a/llvm/test/Transforms/SimplifyCFG/switch-on-const-select.ll b/llvm/test/Transforms/SimplifyCFG/switch-on-const-select.ll
index dec5f80..c33030f 100644
--- a/llvm/test/Transforms/SimplifyCFG/switch-on-const-select.ll
+++ b/llvm/test/Transforms/SimplifyCFG/switch-on-const-select.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -simplifycfg -S | FileCheck %s
+; RUN: opt < %s -simplifycfg -S | FileCheck -enable-var-scope %s
 
 ; Test basic folding to a conditional branch.
 define i32 @foo(i64 %x, i64 %y) nounwind {
@@ -35,7 +35,7 @@ define i32 @bar(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @bar(
 entry:
 ; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.a() [[NUW:#[0-9]+]]
+; CHECK-NEXT: tail call void @bees.a() [[$NUW:#[0-9]+]]
 ; CHECK-NEXT: ret i32 0
     %lt = icmp slt i64 %x, %y
     %qux = select i1 %lt, i32 0, i32 2
@@ -61,7 +61,7 @@ define void @bazz(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @bazz(
 entry:
 ; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.b() [[NUW]]
+; CHECK-NEXT: tail call void @bees.b() [[$NUW]]
 ; CHECK-NEXT: ret void
     %lt = icmp slt i64 %x, %y
     %qux = select i1 %lt, i32 10, i32 12
@@ -86,7 +86,7 @@ define void @quux(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @quux(
 entry:
 ; CHECK-NEXT: entry:
-; CHECK-NEXT: tail call void @bees.a() [[NUW]]
+; CHECK-NEXT: tail call void @bees.a() [[$NUW]]
 ; CHECK-NEXT: ret void
     %lt = icmp slt i64 %x, %y
     %qux = select i1 %lt, i32 0, i32 0
@@ -137,5 +137,5 @@ declare void @llvm.trap() nounwind noreturn
 declare void @bees.a() nounwind
 declare void @bees.b() nounwind
 
-; CHECK: attributes [[NUW]] = { nounwind }
+; CHECK: attributes [[$NUW]] = { nounwind }
 ; CHECK: attributes #1 = { noreturn nounwind }