From: Icenowy Zheng Date: Sat, 6 Oct 2018 15:23:32 +0000 (+0800) Subject: sunxi: fix DRAM gate/reset sequence of H6 X-Git-Tag: v2018.11-rc2~3^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=90de3969be48924114f2d725923e12f32bf7796e;p=platform%2Fkernel%2Fu-boot.git sunxi: fix DRAM gate/reset sequence of H6 Currently the DRAM bus gate and reset is changed at the same time in H6 DRAM initialization code, which disobeys the user manual's programming guide. Fix the sequence by follow the sequence suggested by the user manual (ungate the bus clock after release the reset signal). By some experiments it seems to fix the DRAM size detection failure that rarely happens. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 6b94cf3..5da90a2 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -299,6 +299,8 @@ static void mctl_sys_init(struct dram_para *para) /* Put all DRAM-related blocks to reset state */ clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET); + clrbits_le32(&ccm->dram_gate_reset, BIT(0)); + udelay(5); writel(0, &ccm->dram_gate_reset); clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); @@ -313,7 +315,9 @@ static void mctl_sys_init(struct dram_para *para) /* Configure DRAM mod clock */ writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); - writel(BIT(0) | BIT(RESET_SHIFT), &ccm->dram_gate_reset); + writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset); + udelay(5); + setbits_le32(&ccm->dram_gate_reset, BIT(0)); /* Disable all channels */ writel(0, &mctl_com->maer0);