From: Evan Quan Date: Fri, 25 Sep 2020 06:34:40 +0000 (+0800) Subject: drm/amd/pm: correct pcie spc cap setup X-Git-Tag: v5.15~2259^2~12^2~137 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8f97e221d64d76b8c80b5fa6b41a9a77b8ab1c9f;p=platform%2Fkernel%2Flinux-starfive.git drm/amd/pm: correct pcie spc cap setup Correct Polaris10 pcie spc cap setting. Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index 7eca860..59c199c 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -2865,6 +2865,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) data->pcie_gen_cap = adev->pm.pcie_gen_mask; if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) data->pcie_spc_cap = 20; + else + data->pcie_spc_cap = 16; data->pcie_lane_cap = adev->pm.pcie_mlw_mask; hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */