From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue, 12 Jun 2018 01:19:45 +0000 (-0700)
Subject: Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
X-Git-Tag: v4.19~806
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8efcf34a263965e471e3999904f94d1f6799d42a;p=platform%2Fkernel%2Flinux-rpi3.git

Merge tag 'armsoc-late' of git://git./linux/kernel/git/arm/arm-soc

Pull ARM SoC late updates from Olof Johansson:
 "This is a branch with a few merge requests that either came in late,
  or took a while longer for us to review and merge than usual and thus
  cut it a bit close to the merge window. We stage them in a separate
  branch and if things look good, we still send them up -- and that's
  the case here.

  This is mostly DT additions for Renesas platforms, adding IP block
  descriptions for existing and new SoCs.

  There are also some driver updates for Qualcomm platforms for SMEM/QMI
  and GENI, which is their generalized serial protocol interface"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits)
  soc: qcom: smem: introduce qcom_smem_virt_to_phys()
  soc: qcom: qmi: fix a buffer sizing bug
  MAINTAINERS: Update pattern for qcom_scm
  soc: Unconditionally include qcom Makefile
  soc: qcom: smem: check sooner in qcom_smem_set_global_partition()
  soc: qcom: smem: fix qcom_smem_set_global_partition()
  soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private()
  soc: qcom: smem: byte swap values properly
  soc: qcom: smem: return proper type for cached entry functions
  soc: qcom: smem: fix first cache entry calculation
  soc: qcom: cmd-db: Make endian-agnostic
  drivers: qcom: add command DB driver
  arm64: dts: renesas: salvator-common: Add ADV7482 support
  ARM: dts: r8a7740: Add CEU1
  ARM: dts: r8a7740: Add CEU0
  arm64: dts: renesas: salvator-common: enable VIN
  arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7795-es1: add CSI-2 node
  ...
---

8efcf34a263965e471e3999904f94d1f6799d42a
diff --cc arch/arm/boot/dts/r8a7793.dtsi
index 4f52603,4c29de5..4abecfc
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@@ -1290,9 -1307,29 +1307,27 @@@
  			resets = <&cpg 408>;
  		};
  
+ 		fdp1@fe940000 {
+ 			compatible = "renesas,fdp1";
+ 			reg = <0 0xfe940000 0 0x2400>;
+ 			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 119>;
+ 			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 			resets = <&cpg 119>;
+ 		};
+ 
+ 		fdp1@fe944000 {
+ 			compatible = "renesas,fdp1";
+ 			reg = <0 0xfe944000 0 0x2400>;
+ 			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cpg CPG_MOD 118>;
+ 			power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+ 			resets = <&cpg 118>;
+ 		};
+ 
  		du: display@feb00000 {
  			compatible = "renesas,du-r8a7793";
 -			reg = <0 0xfeb00000 0 0x40000>,
 -			      <0 0xfeb90000 0 0x1c>;
 -			reg-names = "du", "lvds.0";
 +			reg = <0 0xfeb00000 0 0x40000>;
  			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
  				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
  			clocks = <&cpg CPG_MOD 724>,