From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Mon, 23 May 2022 08:34:47 +0000 (+0100)
Subject: Merge tag 'drm-intel-next-2022-05-20' of git://anongit.freedesktop.org/drm/drm-intel... 
X-Git-Tag: v6.1-rc5~176^2~23^2~134
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8ec5c0006c50cb1909c0de0fad137909c1218990;p=platform%2Fkernel%2Flinux-starfive.git

Merge tag 'drm-intel-next-2022-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-intel-gt-next

drm/i915 drm-intel-next -> drm-intel-gt-next cross-merge sync

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

# Conflicts:
#	drivers/gpu/drm/i915/gt/intel_rps.c
#	drivers/gpu/drm/i915/i915_vma.c
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87y1ywbh5y.fsf@intel.com
---

8ec5c0006c50cb1909c0de0fad137909c1218990
diff --cc drivers/gpu/drm/i915/gt/intel_rps.c
index 3bd8415,ce61ceb..fb3f57e
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@@ -1140,15 -1095,13 +1140,16 @@@ static void gen6_rps_init(struct intel_
  	if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
  	    IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
  		u32 ddcc_status = 0;
 +		u32 mult = 1;
  
 +		if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11)
 +			mult = GEN9_FREQ_SCALER;
- 		if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ 		if (snb_pcode_read(rps_to_gt(rps)->uncore,
+ 				   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
  				   &ddcc_status, NULL) == 0)
  			rps->efficient_freq =
 -				clamp_t(u8,
 -					(ddcc_status >> 8) & 0xff,
 +				clamp_t(u32,
 +					((ddcc_status >> 8) & 0xff) * mult,
  					rps->min_freq,
  					rps->max_freq);
  	}
diff --cc drivers/gpu/drm/i915/i915_pci.c
index 664a218,1e5c40f..b9f474d
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@@ -1052,15 -1051,13 +1053,15 @@@ static const struct intel_device_info x
  	.has_4tile = 1, \
  	.has_64k_pages = 1, \
  	.has_guc_deprivilege = 1, \
 +	.has_heci_pxp = 1, \
  	.needs_compact_pt = 1, \
+ 	.has_media_ratio_mode = 1, \
  	.platform_engine_mask = \
  		BIT(RCS0) | BIT(BCS0) | \
  		BIT(VECS0) | BIT(VECS1) | \
 -		BIT(VCS0) | BIT(VCS2)
 +		BIT(VCS0) | BIT(VCS2) | \
 +		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
  
- __maybe_unused
  static const struct intel_device_info dg2_info = {
  	DG2_FEATURES,
  	XE_LPD_FEATURES,
diff --cc drivers/gpu/drm/i915/i915_vma.c
index 79c286f,d077f7b..4f6db53
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@@ -1379,9 -1380,8 +1379,12 @@@ int i915_vma_pin_ww(struct i915_vma *vm
  			goto err_rpm;
  		}
  
 -		work->vm = i915_vm_get(vma->vm);
 +		work->vm = vma->vm;
 +
- 		moving = i915_gem_object_get_moving_fence(vma->obj);
++		err = i915_gem_object_get_moving_fence(vma->obj, &moving);
++		if (err)
++			goto err_rpm;
+ 
  		dma_fence_work_chain(&work->base, moving);
  
  		/* Allocate enough page directories to used PTE */