From: Krzysztof Parzyszek Date: Wed, 5 Dec 2018 21:14:51 +0000 (+0000) Subject: [Hexagon] Add intrinsics for Hexagon V66 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8eb394d7643e20d7b75225a47a11400ab505439d;p=platform%2Fupstream%2Fllvm.git [Hexagon] Add intrinsics for Hexagon V66 llvm-svn: 348413 --- diff --git a/llvm/include/llvm/IR/IntrinsicsHexagon.td b/llvm/include/llvm/IR/IntrinsicsHexagon.td index 889662d..ecc69a6 100644 --- a/llvm/include/llvm/IR/IntrinsicsHexagon.td +++ b/llvm/include/llvm/IR/IntrinsicsHexagon.td @@ -637,6 +637,18 @@ class Hexagon_i64_i32i32_Intrinsic [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], [IntrNoMem]>; +// tag : V6_lo +class Hexagon_v16i32_v32i32_Intrinsic + : Hexagon_Intrinsic; + +// tag : V6_lo +class Hexagon_v32i32_v64i32_Intrinsic + : Hexagon_Intrinsic; + // tag : S2_shuffoh class Hexagon_i64_i64i64_Intrinsic : Hexagon_Intrinsic [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty], [IntrNoMem]>; -// tag : V6_lo -class Hexagon_v16i32_v32i32_Intrinsic - : Hexagon_Intrinsic; - -// tag : V6_lo -class Hexagon_v32i32_v64i32_Intrinsic - : Hexagon_Intrinsic; - // tag : V6_vlutvwhi class Hexagon_v32i32_v16i32v16i32i32_Intrinsic : Hexagon_Intrinsic [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], [IntrNoMem]>; +// tag : V6_vaddcarrysat +class Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic + : Hexagon_Intrinsic; + +// tag : V6_vaddcarrysat +class Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic + : Hexagon_Intrinsic; + // tag : V6_vlutvvb_oracc class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic : Hexagon_Intrinsic [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty], [IntrNoMem]>; +// tag : F2_dfsub +class Hexagon_double_doubledouble_Intrinsic + : Hexagon_Intrinsic; + // tag : V6_vmpyowh_sacc class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic : Hexagon_Intrinsic; def int_hexagon_A6_vcmpbeq_notany : Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; +// V66 Scalar Instructions. + +def int_hexagon_F2_dfsub : +Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub">; + +def int_hexagon_F2_dfadd : +Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd">; + +def int_hexagon_M2_mnaci : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">; + +def int_hexagon_S2_mask : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask">; + // V60 HVX Instructions. def int_hexagon_V6_veqb_or : @@ -6296,3 +6328,29 @@ Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">; def int_hexagon_V6_vabsb_sat_128B : Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; +// V66 HVX Instructions. + +def int_hexagon_V6_vaddcarrysat : +Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">; + +def int_hexagon_V6_vaddcarrysat_128B : +Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">; + +def int_hexagon_V6_vasr_into : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">; + +def int_hexagon_V6_vasr_into_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">; + +def int_hexagon_V6_vsatdw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">; + +def int_hexagon_V6_vsatdw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">; + +def int_hexagon_V6_vrotr : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">; + +def int_hexagon_V6_vrotr_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">; + diff --git a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td index 65cca41..2346fa5 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td +++ b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td @@ -1737,6 +1737,17 @@ def: Pat<(int_hexagon_S6_vsplatrbp IntRegs:$src1), def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65]>; +// V66 Scalar Instructions. + +def: Pat<(int_hexagon_F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>; +def: Pat<(int_hexagon_F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>; +def: Pat<(int_hexagon_M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV66]>; +def: Pat<(int_hexagon_S2_mask u5_0ImmPred:$src1, u5_0ImmPred:$src2), + (S2_mask u5_0ImmPred:$src1, u5_0ImmPred:$src2)>, Requires<[HasV66]>; + // V60 HVX Instructions. def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), @@ -3305,3 +3316,22 @@ def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>; + +// V66 HVX Instructions. + +def: Pat<(int_hexagon_V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddcarrysat_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasr_into_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsatdw HvxVR:$src1, HvxVR:$src2), + (V6_vsatdw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsatdw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsatdw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrotr HvxVR:$src1, HvxVR:$src2), + (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrotr_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>; diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v66.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v66.ll new file mode 100644 index 0000000..2732b9c --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v66.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv66 < %s | FileCheck %s + +; CHECK-LABEL: @test1 +; CHECK: r0 -= mpyi(r1,r2) +define i32 @test1(i32 %rx, i32 %rs, i32 %rt) local_unnamed_addr #0 { +entry: + %v0 = tail call i32 @llvm.hexagon.M2.mnaci(i32 %rx, i32 %rs, i32 %rt) + ret i32 %v0 +} + +declare i32 @llvm.hexagon.M2.mnaci(i32, i32, i32) #1 + +; CHECK-LABEL: @test2 +; CHECK: r1:0 = dfadd(r1:0,r3:2) +define double @test2(double %rss, double %rtt) local_unnamed_addr #0 { +entry: + %v0 = tail call double @llvm.hexagon.F2.dfadd(double %rss, double %rtt) + ret double %v0 +} + +declare double @llvm.hexagon.F2.dfadd(double, double) #1 + +; CHECK-LABEL: @test3 +; CHECK: r1:0 = dfsub(r1:0,r3:2) +define double @test3(double %rss, double %rtt) local_unnamed_addr #0 { +entry: + %v0 = tail call double @llvm.hexagon.F2.dfsub(double %rss, double %rtt) + ret double %v0 +} + +declare double @llvm.hexagon.F2.dfsub(double, double) #1 + +; CHECK-LABEL: @test4 +; CHECK: r0 = mask(#1,#2) +define i32 @test4() local_unnamed_addr #0 { +entry: + %v0 = tail call i32 @llvm.hexagon.S2.mask(i32 1, i32 2) + ret i32 %v0 +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.hexagon.S2.mask(i32, i32) #1 + +attributes #0 = { nounwind readnone "target-cpu"="hexagonv66" "target-features"="-hvx,-long-calls" } +attributes #1 = { nounwind readnone }