From: Craig Topper <craig.topper@sifive.com>
Date: Wed, 14 Dec 2022 20:38:41 +0000 (-0800)
Subject: [RISCV] Add missing signext attribute to test. NFC
X-Git-Tag: upstream/17.0.6~23791
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8eabbd3cd2268e3a403b960f4f744386dccc26d6;p=platform%2Fupstream%2Fllvm.git

[RISCV] Add missing signext attribute to test. NFC

The other operands in this function had it and every other test
in the file has it. So I assume this was a mistake.
---

diff --git a/llvm/test/CodeGen/RISCV/select-binop-identity.ll b/llvm/test/CodeGen/RISCV/select-binop-identity.ll
index c4a6b40..7dee8f8 100644
--- a/llvm/test/CodeGen/RISCV/select-binop-identity.ll
+++ b/llvm/test/CodeGen/RISCV/select-binop-identity.ll
@@ -12,7 +12,7 @@
 ; We can reverse this for and/or/xor. Allowing us to pull the binop into
 ; the basic block we create when we expand select.
 
-define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 %y) {
+define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
 ; RV32I-LABEL: and_select_all_ones_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, a0, -1
@@ -25,7 +25,6 @@ define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 %
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; SFB64-LABEL: and_select_all_ones_i32:
@@ -35,7 +34,7 @@ define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 %
 ; SFB64-NEXT:  # %bb.1:
 ; SFB64-NEXT:    mv a1, a2
 ; SFB64-NEXT:  .LBB0_2:
-; SFB64-NEXT:    sext.w a0, a1
+; SFB64-NEXT:    mv a0, a1
 ; SFB64-NEXT:    ret
   %a = select i1 %c, i32 %x, i32 -1
   %b = and i32 %a, %y