From: Rob Clark Date: Fri, 31 May 2019 14:07:57 +0000 (-0700) Subject: freedreno/a6xx: fix GPU crash on small render targets X-Git-Tag: upstream/19.3.0~5977 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8eaa2d502131bdce874603f522eabc4a5719f2e6;p=platform%2Fupstream%2Fmesa.git freedreno/a6xx: fix GPU crash on small render targets Fixes dEQP-GLES2.functional.multisampled_render_to_texture.readpixels Signed-off-by: Rob Clark Acked-by: Eric Anholt --- diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index a00e444..6ad0bc6 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -640,6 +640,13 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring) blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx); blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy); + /* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for + * small render targets. But since we align pitch to binw I think + * we can get away avoiding GPU hangs a simpler way, by just rounding + * up the blit scissor: + */ + blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw); + OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2); OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |