From: Alex Bradbury <asb@igalia.com>
Date: Thu, 18 May 2023 14:01:48 +0000 (+0100)
Subject: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled
X-Git-Tag: upstream/17.0.6~8011
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8e82376863460f6dc2dbb7fe6754af3ba69cc9c4;p=platform%2Fupstream%2Fllvm.git

[clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

Now that codegen support for zhinx in landed (D149811), we should set
HasLegalHalfType=true for zhinx (see D145071 for the patch doing this
for zfh).

Differential Revision: https://reviews.llvm.org/D150777
---

diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index bb61d75..5318cf5 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -320,7 +320,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   if (ABI.empty())
     ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
     HasLegalHalfType = true;
 
   return true;
diff --git a/clang/test/CodeGen/RISCV/Float16-arith.c b/clang/test/CodeGen/RISCV/Float16-arith.c
index baedc07..97faa48 100644
--- a/clang/test/CodeGen/RISCV/Float16-arith.c
+++ b/clang/test/CodeGen/RISCV/Float16-arith.c
@@ -42,12 +42,9 @@ _Float16 x, y, z;
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:    [[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:    [[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:    [[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:    [[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:    [[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:    [[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:    store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:    [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:    store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:    ret void
 //
 void f16_add() {