From: Thomas Zimmermann <tzimmermann@suse.de>
Date: Sat, 5 Nov 2022 15:02:42 +0000 (+0100)
Subject: Merge drm/drm-next into drm-misc-next
X-Git-Tag: v6.6.17~3937^2~23^2~1384
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8e4e4c2f53ffcb0ef746dc3b87ce1a57c5c94c7d;p=platform%2Fkernel%2Flinux-rpi.git

Merge drm/drm-next into drm-misc-next

Backmerging drm/drm-next to get the latest changes in the xlnx driver.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---

8e4e4c2f53ffcb0ef746dc3b87ce1a57c5c94c7d
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index df6fd6d,69e105f..59cf642
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@@ -139,10 -116,21 +139,17 @@@ static int amdgpu_vm_sdma_commit(struc
  				   DMA_RESV_USAGE_BOOKKEEP);
  	}
  
- 	if (fence && !p->immediate)
+ 	if (fence && !p->immediate) {
+ 		/*
+ 		 * Most hw generations now have a separate queue for page table
+ 		 * updates, but when the queue is shared with userspace we need
+ 		 * the extra CPU round trip to correctly flush the TLB.
+ 		 */
+ 		set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags);
  		swap(*fence, f);
+ 	}
  	dma_fence_put(f);
  	return 0;
 -
 -error:
 -	amdgpu_job_free(p->job);
 -	return r;
  }
  
  /**
diff --cc include/drm/gpu_scheduler.h
index e40baef,ca11716..cec147f
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@@ -32,8 -32,15 +32,17 @@@
  
  #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
  
+ /**
+  * DRM_SCHED_FENCE_DONT_PIPELINE - Prefent dependency pipelining
+  *
+  * Setting this flag on a scheduler fence prevents pipelining of jobs depending
+  * on this fence. In other words we always insert a full CPU round trip before
+  * dependen jobs are pushed to the hw queue.
+  */
+ #define DRM_SCHED_FENCE_DONT_PIPELINE	DMA_FENCE_FLAG_USER_BITS
+ 
 +enum dma_resv_usage;
 +struct dma_resv;
  struct drm_gem_object;
  
  struct drm_gpu_scheduler;