From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Wed, 11 Jun 2008 11:03:34 +0000 (+0000)
Subject: Allocate register pair for 64-bit registers on 32-bit host.
X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~14556
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8df1ca4ba51fc3bfccc3d901584b316ae2e60bb9;p=sdk%2Femulator%2Fqemu.git

Allocate register pair for 64-bit registers on 32-bit host.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4730 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/tcg/tcg.c b/tcg/tcg.c
index b4b8d8e..e976054 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -423,7 +423,7 @@ TCGv tcg_temp_new_internal(TCGType type, int temp_local)
         idx = s->nb_temps;
 #if TCG_TARGET_REG_BITS == 32
         if (type == TCG_TYPE_I64) {
-            tcg_temp_alloc(s, s->nb_temps + 1);
+            tcg_temp_alloc(s, s->nb_temps + 2);
             ts = &s->temps[s->nb_temps];
             ts->base_type = type;
             ts->type = TCG_TYPE_I32;
@@ -1961,7 +1961,7 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
             break;
         }
         args += def->nb_args;
-    next: ;
+    next:
         if (search_pc >= 0 && search_pc < s->code_ptr - gen_code_buf) {
             return op_index;
         }