From: Kenneth Graunke Date: Wed, 23 Oct 2019 22:38:52 +0000 (-0700) Subject: iris: Rework edgeflag handling X-Git-Tag: upstream/19.3.0~650 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8dadef2ec54b23a1f34cb0e5f1ff7f60b5937e85;p=platform%2Fupstream%2Fmesa.git iris: Rework edgeflag handling We were relying on specific pass ordering in st to avoid setting inputs_read/outputs_written for edge flags. Instead, just assume that it happens and throw out the results we don't want. We should probably revisit this and try and add a vertex element property like I originally wanted so we can avoid having it be associated with the VS altogether. --- diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 74a66f4..6833d36 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -281,6 +281,8 @@ struct iris_uncompiled_shader { /** Should we use ALT mode for math? Useful for ARB programs. */ bool use_alt_mode; + bool needs_edge_flag; + /** Constant data scraped from the shader by nir_opt_large_constants */ struct pipe_resource *const_data; diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 6f2b320..2189825 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -186,6 +186,28 @@ iris_lower_storage_image_derefs(nir_shader *nir) // XXX: need unify_interfaces() at link time... /** + * Undo nir_lower_passthrough_edgeflags but keep the inputs_read flag. + */ +static bool +iris_fix_edge_flags(nir_shader *nir) +{ + if (nir->info.stage != MESA_SHADER_VERTEX) + return false; + + nir_foreach_variable(var, &nir->outputs) { + if (var->data.location == VARYING_SLOT_EDGE) { + var->data.mode = nir_var_shader_temp; + nir->info.outputs_written &= ~VARYING_BIT_EDGE; + nir->info.inputs_read &= ~VERT_BIT_EDGEFLAG; + nir_fixup_deref_modes(nir); + return true; + } + } + + return false; +} + +/** * Fix an uncompiled shader's stream output info. * * Core Gallium stores output->register_index as a "slot" number, where @@ -1042,22 +1064,17 @@ iris_update_compiled_vs(struct iris_context *ice) const bool needs_sgvs_element = uses_draw_params || vs_prog_data->uses_instanceid || vs_prog_data->uses_vertexid; - bool needs_edge_flag = false; - nir_foreach_variable(var, &ish->nir->inputs) { - if (var->data.location == VERT_ATTRIB_EDGEFLAG) - needs_edge_flag = true; - } if (ice->state.vs_uses_draw_params != uses_draw_params || ice->state.vs_uses_derived_draw_params != uses_derived_draw_params || - ice->state.vs_needs_edge_flag != needs_edge_flag) { + ice->state.vs_needs_edge_flag != ish->needs_edge_flag) { ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS | IRIS_DIRTY_VERTEX_ELEMENTS; } ice->state.vs_uses_draw_params = uses_draw_params; ice->state.vs_uses_derived_draw_params = uses_derived_draw_params; ice->state.vs_needs_sgvs_element = needs_sgvs_element; - ice->state.vs_needs_edge_flag = needs_edge_flag; + ice->state.vs_needs_edge_flag = ish->needs_edge_flag; } } @@ -1992,6 +2009,8 @@ iris_create_uncompiled_shader(struct pipe_context *ctx, if (!ish) return NULL; + ish->needs_edge_flag = iris_fix_edge_flags(nir); + brw_preprocess_nir(screen->compiler, nir, NULL); NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo);