From: Mike Frysinger Date: Sat, 31 Mar 2012 18:48:20 +0000 (+0000) Subject: sim: bfin: fix typo in BF54x SIC init X-Git-Tag: sid-snapshot-20120401~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8d72c97073a410854647c55c5c8915160faf2c62;p=external%2Fbinutils.git sim: bfin: fix typo in BF54x SIC init The current code triggers a warning: dv-bfin_sic.c: In function 'bfin_sic_finish': dv-bfin_sic.c:930:41: warning: operation on 'sic->.bf54x.iwr1' may be undefined [-Wsequence-point] This points out the IWR2 register was not being setup because of a typo. Signed-off-by: Mike Frysinger --- diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index cdaf5ba..973b788 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,5 +1,9 @@ 2012-03-31 Mike Frysinger + * dv-bfin_sic.c (bfin_sic_finish): Change iwr1 to iwr2. + +2012-03-31 Mike Frysinger + * devices.c: Include devices.h. 2012-03-24 Mike Frysinger diff --git a/sim/bfin/dv-bfin_sic.c b/sim/bfin/dv-bfin_sic.c index 277e4e1..a565575 100644 --- a/sim/bfin/dv-bfin_sic.c +++ b/sim/bfin/dv-bfin_sic.c @@ -926,7 +926,7 @@ bfin_sic_finish (struct hw *me) /* Initialize the SIC. */ sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0; sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0; - sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr1 = 0xFFFFFFFF; + sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr2 = 0xFFFFFFFF; sic->bf54x.iar0 = 0x10000000; sic->bf54x.iar1 = 0x33322221; sic->bf54x.iar2 = 0x66655444;