From: Marek Szyprowski Date: Wed, 15 May 2019 10:58:27 +0000 (+0200) Subject: ARM: defconfig: enable I-Cache line size workaround on Exynos systems X-Git-Tag: submit/tizen/20190611.014400^0 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8d40f3e556f9473254b6ac1dc0c0f564f1cdcd08;p=platform%2Fkernel%2Flinux-exynos.git ARM: defconfig: enable I-Cache line size workaround on Exynos systems All Exynos big.LITTLE system suffer from I-Cache line size mismatch between CPU cores, so enable workaround for it in exynos_defconfig and tizen_odroid_defconfig. Signed-off-by: Marek Szyprowski Change-Id: I0f324a5832e1ef47999f7b8d4ddd4a29db0ee176 --- diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 93c5182c91a9..24c619357249 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -10,6 +10,7 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_EXYNOS3=y CONFIG_EXYNOS5420_MCPM=y +CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y CONFIG_SMP=y CONFIG_BIG_LITTLE=y CONFIG_NR_CPUS=8 diff --git a/arch/arm/configs/tizen_odroid_defconfig b/arch/arm/configs/tizen_odroid_defconfig index 73e5a96b2dd2..17d76057ae12 100644 --- a/arch/arm/configs/tizen_odroid_defconfig +++ b/arch/arm/configs/tizen_odroid_defconfig @@ -22,6 +22,7 @@ CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_EXYNOS3=y CONFIG_EXYNOS5420_MCPM=y # CONFIG_ARM_ERRATA_643719 is not set +CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y CONFIG_SMP=y CONFIG_BIG_LITTLE=y CONFIG_NR_CPUS=8