From: meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue, 12 Apr 2016 19:25:56 +0000 (+0000)
Subject: [gcc]
X-Git-Tag: upstream/6.1~201
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8ca5a97dff13029f7f4901ffd303cfa852b86ac3;p=platform%2Fupstream%2Flinaro-gcc.git

[gcc]
2016-04-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/70680
	* config/rs6000/rs6000.md (ieee_128bit_vsx_neg<mode>2_internal):
	Do not use "=" constraint on an input constraint.
	(ieee_128bit_vsx_abs<mode>2_internal): Likewise.
	(ieee_128bit_vsx_nabs<mode>2_internal): Likewise.
	(ieee_128bit_vsx_nabs<mode>2): Correct splitter so that it
	generates (neg (abs ...)) instead of (abs ...).

[gcc/testsuite]
2016-04-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/70680
	* gcc.target/powerpc/pr70640.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234910 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7222254..d132dcf 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2016-04-12  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/70680
+	* config/rs6000/rs6000.md (ieee_128bit_vsx_neg<mode>2_internal):
+	Do not use "=" constraint on an input constraint.
+	(ieee_128bit_vsx_abs<mode>2_internal): Likewise.
+	(ieee_128bit_vsx_nabs<mode>2_internal): Likewise.
+	(ieee_128bit_vsx_nabs<mode>2): Correct splitter so that it
+	generates (neg (abs ...)) instead of (abs ...).
+
 2016-04-12  Jakub Jelinek  <jakub@redhat.com>
 
 	PR rtl-optimization/70596
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ef1dea8..849b19a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7261,7 +7261,7 @@
 (define_insn "*ieee_128bit_vsx_neg<mode>2_internal"
   [(set (match_operand:IEEE128 0 "register_operand" "=wa")
 	(neg:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
-   (use (match_operand:V16QI 2 "register_operand" "=v"))]
+   (use (match_operand:V16QI 2 "register_operand" "v"))]
   "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
   "xxlxor %x0,%x1,%x2"
   [(set_attr "type" "vecsimple")])
@@ -7290,7 +7290,7 @@
 (define_insn "*ieee_128bit_vsx_abs<mode>2_internal"
   [(set (match_operand:IEEE128 0 "register_operand" "=wa")
 	(abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
-   (use (match_operand:V16QI 2 "register_operand" "=v"))]
+   (use (match_operand:V16QI 2 "register_operand" "v"))]
   "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
   "xxlandc %x0,%x1,%x2"
   [(set_attr "type" "vecsimple")])
@@ -7306,7 +7306,7 @@
   "#"
   "&& 1"
   [(parallel [(set (match_dup 0)
-		   (abs:IEEE128 (match_dup 1)))
+		   (neg:IEEE128 (abs:IEEE128 (match_dup 1))))
 	      (use (match_dup 2))])]
 {
   if (GET_CODE (operands[2]) == SCRATCH)
@@ -7323,7 +7323,7 @@
 	(neg:IEEE128
 	 (abs:IEEE128
 	  (match_operand:IEEE128 1 "register_operand" "wa"))))
-   (use (match_operand:V16QI 2 "register_operand" "=v"))]
+   (use (match_operand:V16QI 2 "register_operand" "v"))]
   "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
   "xxlor %x0,%x1,%x2"
   [(set_attr "type" "vecsimple")])
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 171c696..996117b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-04-12  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/70680
+	* gcc.target/powerpc/pr70640.c: New test.
+
 2016-04-12  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	PR c++/68722
diff --git a/gcc/testsuite/gcc.target/powerpc/pr70640.c b/gcc/testsuite/gcc.target/powerpc/pr70640.c
new file mode 100644
index 0000000..7b991c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr70640.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_float128_sw_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-O2 -mcpu=power8 -mfloat128" } */
+
+__float128 foo (__float128 a) { return -a; }
+
+/* { dg-final { scan-assembler "xxlorc" } } */
+/* { dg-final { scan-assembler "xxlxor" } } */
+/* { dg-final { scan-assembler "vslb"   } } */
+/* { dg-final { scan-assembler "vsldoi" } } */