From: Kenneth Graunke Date: Sat, 9 Apr 2011 06:51:21 +0000 (-0700) Subject: i965: Add depth buffer support on Ivybridge. X-Git-Tag: mesa-7.11-rc1~680 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8c8985bdd714f43a96ce922a7c0284d50aec3d1a;p=platform%2Fupstream%2Fmesa.git i965: Add depth buffer support on Ivybridge. This also disables the HiZ and separate stencil buffers. We still need to implement stencil. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt --- diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile index 0c6313a..4e80785 100644 --- a/src/mesa/drivers/dri/i965/Makefile +++ b/src/mesa/drivers/dri/i965/Makefile @@ -100,6 +100,7 @@ DRIVER_SOURCES = \ gen7_cc_state.c \ gen7_clip_state.c \ gen7_disable.c \ + gen7_misc_state.c \ gen7_sf_state.c \ gen7_urb.c \ gen7_viewport_state.c \ diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2a195d8..f07f126 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1245,7 +1245,7 @@ #define _3DSTATE_DRAWING_RECTANGLE 0x7900 #define _3DSTATE_BLEND_CONSTANT_COLOR 0x7901 #define _3DSTATE_CHROMA_KEY 0x7904 -#define _3DSTATE_DEPTH_BUFFER 0x7905 +#define _3DSTATE_DEPTH_BUFFER 0x7905 /* GEN4-6 */ #define _3DSTATE_POLY_STIPPLE_OFFSET 0x7906 #define _3DSTATE_POLY_STIPPLE_PATTERN 0x7907 #define _3DSTATE_LINE_STIPPLE_PATTERN 0x7908 @@ -1270,7 +1270,12 @@ #define _3DSTATE_STENCIL_BUFFER 0x790e /* ILK, SNB */ #define _3DSTATE_HIER_DEPTH_BUFFER 0x790f /* ILK, SNB */ -#define _3DSTATE_CLEAR_PARAMS 0x7910 /* ILK+ */ +#define GEN7_3DSTATE_CLEAR_PARAMS 0x7804 +#define GEN7_3DSTATE_DEPTH_BUFFER 0x7805 +#define GEN7_3DSTATE_STENCIL_BUFFER 0x7806 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER 0x7807 + +#define _3DSTATE_CLEAR_PARAMS 0x7910 /* ILK, SNB */ # define DEPTH_CLEAR_VALID (1 << 15) /* DW1: depth clear value */ diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index bb2b496d..99e63e0 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -111,6 +111,7 @@ extern const struct brw_tracked_state gen6_vs_constants; extern const struct brw_tracked_state gen6_vs_state; extern const struct brw_tracked_state gen6_wm_constants; extern const struct brw_tracked_state gen6_wm_state; +extern const struct brw_tracked_state gen7_depthbuffer; extern const struct brw_tracked_state gen7_blend_state_pointer; extern const struct brw_tracked_state gen7_cc_state_pointer; extern const struct brw_tracked_state gen7_cc_viewport_state_pointer; @@ -183,4 +184,8 @@ void brw_create_constant_surface(struct brw_context *brw, uint32_t get_attr_override(struct brw_context *brw, int fs_attr, int two_side_color); +/* gen7_misc_state.c */ +unsigned int +gen7_depth_format(struct brw_context *brw); + #endif diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index e444e2f..73aca31 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -219,7 +219,7 @@ const struct brw_tracked_state *gen7_atoms[] = &gen6_scissor_state, - &brw_depthbuffer, + &gen7_depthbuffer, &brw_polygon_stipple, &brw_polygon_stipple_offset, diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c new file mode 100644 index 0000000..adcb31f --- /dev/null +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -0,0 +1,122 @@ +/* + * Copyright © 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "intel_batchbuffer.h" +#include "intel_regions.h" +#include "brw_context.h" +#include "brw_state.h" +#include "brw_defines.h" + +unsigned int +gen7_depth_format(struct brw_context *brw) +{ + struct intel_region *region = brw->state.depth_region; + struct intel_context *intel = &brw->intel; + + if (region == NULL) + return BRW_DEPTHFORMAT_D32_FLOAT; + + switch (region->cpp) { + case 2: + return BRW_DEPTHFORMAT_D16_UNORM; + case 4: + if (intel->depth_buffer_is_float) + return BRW_DEPTHFORMAT_D32_FLOAT; + else + return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; + default: + assert(!"Should not get here."); + } + return 0; +} + +static void emit_depthbuffer(struct brw_context *brw) +{ + struct intel_region *region = brw->state.depth_region; + struct intel_context *intel = &brw->intel; + struct gl_context *ctx = &intel->ctx; + + if (region == NULL) { + BEGIN_BATCH(7); + OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); + OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | + (BRW_SURFACE_NULL << 29)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + assert(region->tiling == I915_TILING_Y); + + BEGIN_BATCH(7); + OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); + OUT_BATCH(((region->pitch * region->cpp) - 1) | + (gen7_depth_format(brw) << 18) | + (0 << 22) /* no HiZ buffer */ | + (0 << 27) /* no stencil write */ | + ((ctx->Depth.Mask != 0) << 28) | + (BRW_SURFACE_2D << 29)); + OUT_RELOC(region->buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + 0); + OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } + + BEGIN_BATCH(4); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + BEGIN_BATCH(4); + OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} + +/** + * \see brw_context.state.depth_region + */ +const struct brw_tracked_state gen7_depthbuffer = { + .dirty = { + .mesa = 0, + .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH, + .cache = 0, + }, + .emit = emit_depthbuffer, +}; diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index 37c628d..d1bf8a8 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -126,9 +126,10 @@ upload_sf_state(struct brw_context *brw) /* _NEW_BUFFERS */ bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0; - /* FINISHME: Depth Buffer Surface Format? */ dw1 = GEN6_SF_STATISTICS_ENABLE | GEN6_SF_VIEWPORT_TRANSFORM_ENABLE; + dw1 |= (gen7_depth_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); + /* _NEW_POLYGON */ if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo) dw1 |= GEN6_SF_WINDING_CCW; @@ -257,7 +258,8 @@ const struct brw_tracked_state gen7_sf_state = { _NEW_SCISSOR | _NEW_BUFFERS | _NEW_POINT), - .brw = BRW_NEW_CONTEXT, + .brw = (BRW_NEW_CONTEXT | + BRW_NEW_DEPTH_BUFFER), .cache = CACHE_NEW_VS_PROG }, .emit = upload_sf_state,