From: gjl Date: Tue, 6 Dec 2011 15:04:09 +0000 (+0000) Subject: libgcc/ X-Git-Tag: upstream/4.9.2~15700 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8c8193e1f5f49c161d53cfff7494e2e4f7704731;p=platform%2Fupstream%2Flinaro-gcc.git libgcc/ Forward-port from gcc-4_6-branch r181936 2011-12-02. PR target/51345 PR target/51002 * config/avr/lib1funcs.S (__prologue_saves__, __epilogue_restores__, __divdi3_moddi3): Enclose parts using __SP_H__ in !defined (__AVR_HAVE_8BIT_SP__). Add FIXME comments. gcc/ Forward-port from gcc-4_6-branch r181936 2011-12-02. PR target/51002 * config/avr/avr.md (movhi_sp_r): Set insn condition to !AVR_HAVE_8BIT_SP. * config/avr/avr.c (output_movhi): Use "clr%B0" instead of "in %B0,__SP_H__" if AVR_HAVE_8BIT_SP. (avr_file_start): Only print "__SP_H__ = 0x3e" if !AVR_HAVE_8BIT_SP. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@182052 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2375361..2ddce7a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,16 @@ 2011-12-06 Georg-Johann Lay + Forward-port from gcc-4_6-branch r181936 2011-12-02. + + PR target/51002 + * config/avr/avr.md (movhi_sp_r): Set insn condition to + !AVR_HAVE_8BIT_SP. + * config/avr/avr.c (output_movhi): Use "clr%B0" instead of "in + %B0,__SP_H__" if AVR_HAVE_8BIT_SP. + (avr_file_start): Only print "__SP_H__ = 0x3e" if !AVR_HAVE_8BIT_SP. + +2011-12-06 Georg-Johann Lay + PR target/51409 PR target/49868 * config/avr/avr.h (ADDR_SPACE_PGM, ADDR_SPACE_PGM1, diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index a6ef59f..8b85b5c 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -2875,78 +2875,77 @@ output_movqi (rtx insn, rtx operands[], int *l) const char * -output_movhi (rtx insn, rtx operands[], int *l) +output_movhi (rtx insn, rtx xop[], int *plen) { - int dummy; - rtx dest = operands[0]; - rtx src = operands[1]; - int *real_l = l; + rtx dest = xop[0]; + rtx src = xop[1]; + + gcc_assert (GET_MODE_SIZE (GET_MODE (dest)) == 2); if (avr_mem_pgm_p (src) || avr_mem_pgm_p (dest)) { - return avr_out_lpm (insn, operands, real_l); + return avr_out_lpm (insn, xop, plen); } - if (!l) - l = &dummy; - - if (register_operand (dest, HImode)) + if (REG_P (dest)) { - if (register_operand (src, HImode)) /* mov r,r */ - { - if (test_hard_reg_class (STACK_REG, dest)) - { - if (AVR_HAVE_8BIT_SP) - return *l = 1, AS2 (out,__SP_L__,%A1); - /* Use simple load of stack pointer if no interrupts are - used. */ - else if (TARGET_NO_INTERRUPTS) - return *l = 2, (AS2 (out,__SP_H__,%B1) CR_TAB - AS2 (out,__SP_L__,%A1)); - *l = 5; - return (AS2 (in,__tmp_reg__,__SREG__) CR_TAB - "cli" CR_TAB - AS2 (out,__SP_H__,%B1) CR_TAB - AS2 (out,__SREG__,__tmp_reg__) CR_TAB - AS2 (out,__SP_L__,%A1)); - } - else if (test_hard_reg_class (STACK_REG, src)) - { - *l = 2; - return (AS2 (in,%A0,__SP_L__) CR_TAB - AS2 (in,%B0,__SP_H__)); - } + if (REG_P (src)) /* mov r,r */ + { + if (test_hard_reg_class (STACK_REG, dest)) + { + if (AVR_HAVE_8BIT_SP) + return avr_asm_len ("out __SP_L__,%A1", xop, plen, -1); + + /* Use simple load of SP if no interrupts are used. */ + + return TARGET_NO_INTERRUPTS + ? avr_asm_len ("out __SP_H__,%B1" CR_TAB + "out __SP_L__,%A1", xop, plen, -2) + + : avr_asm_len ("in __tmp_reg__,__SREG__" CR_TAB + "cli" CR_TAB + "out __SP_H__,%B1" CR_TAB + "out __SREG__,__tmp_reg__" CR_TAB + "out __SP_L__,%A1", xop, plen, -5); + } + else if (test_hard_reg_class (STACK_REG, src)) + { + return AVR_HAVE_8BIT_SP + ? avr_asm_len ("in %A0,__SP_L__" CR_TAB + "clr %B0", xop, plen, -2) + + : avr_asm_len ("in %A0,__SP_L__" CR_TAB + "in %B0,__SP_H__", xop, plen, -2); + } - if (AVR_HAVE_MOVW) - { - *l = 1; - return (AS2 (movw,%0,%1)); - } - else - { - *l = 2; - return (AS2 (mov,%A0,%A1) CR_TAB - AS2 (mov,%B0,%B1)); - } - } + return AVR_HAVE_MOVW + ? avr_asm_len ("movw %0,%1", xop, plen, -1) + + : avr_asm_len ("mov %A0,%A1" CR_TAB + "mov %B0,%B1", xop, plen, -2); + } /* REG_P (src) */ else if (CONSTANT_P (src)) { - return output_reload_inhi (operands, NULL, real_l); + return output_reload_inhi (xop, NULL, plen); + } + else if (MEM_P (src)) + { + return out_movhi_r_mr (insn, xop, plen); /* mov r,m */ } - else if (GET_CODE (src) == MEM) - return out_movhi_r_mr (insn, operands, real_l); /* mov r,m */ } - else if (GET_CODE (dest) == MEM) + else if (MEM_P (dest)) { rtx xop[2]; xop[0] = dest; xop[1] = src == const0_rtx ? zero_reg_rtx : src; - return out_movhi_mr_r (insn, xop, real_l); + return out_movhi_mr_r (insn, xop, plen); } + fatal_insn ("invalid insn:", insn); + return ""; } @@ -7272,16 +7271,19 @@ avr_file_start (void) default_file_start (); + if (!AVR_HAVE_8BIT_SP) + fprintf (asm_out_file, + "__SP_H__ = 0x%02x\n" + -sfr_offset + SP_ADDR + 1); + fprintf (asm_out_file, - "__SREG__ = 0x%02x\n" - "__SP_H__ = 0x%02x\n" "__SP_L__ = 0x%02x\n" + "__SREG__ = 0x%02x\n" "__RAMPZ__ = 0x%02x\n" "__tmp_reg__ = %d\n" "__zero_reg__ = %d\n", - -sfr_offset + SREG_ADDR, - -sfr_offset + SP_ADDR + 1, -sfr_offset + SP_ADDR, + -sfr_offset + SREG_ADDR, -sfr_offset + RAMPZ_ADDR, TMP_REGNO, ZERO_REGNO); diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index bddfe93..1c79894 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -620,7 +620,7 @@ (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r,r") (match_operand:HI 2 "const_int_operand" "L,P")] UNSPECV_WRITE_SP))] - "" + "!AVR_HAVE_8BIT_SP" "@ out __SP_H__,%B1\;out __SP_L__,%A1 cli\;out __SP_H__,%B1\;sei\;out __SP_L__,%A1" diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 9ad344e..cde3853 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,13 @@ +2011-12-06 Georg-Johann Lay + + Forward-port from gcc-4_6-branch r181936 2011-12-02. + + PR target/51345 + PR target/51002 + * config/avr/lib1funcs.S (__prologue_saves__, + __epilogue_restores__, __divdi3_moddi3): Enclose parts using + __SP_H__ in !defined (__AVR_HAVE_8BIT_SP__). Add FIXME comments. + 2011-12-04 Iain Sandoe * config/rs6000/t-darwin64 (LIB2ADD): Add fp and gp save routines. diff --git a/libgcc/config/avr/lib1funcs.S b/libgcc/config/avr/lib1funcs.S index c592c4c..3545d09 100644 --- a/libgcc/config/avr/lib1funcs.S +++ b/libgcc/config/avr/lib1funcs.S @@ -1149,7 +1149,14 @@ DEFUN __divdi3_moddi3 4: ;; Epilogue: Restore the Z = 12 Registers and return in r28, __SP_L__ +#if defined (__AVR_HAVE_8BIT_SP__) +;; FIXME: __AVR_HAVE_8BIT_SP__ is set on device level, not on core level +;; so this lines are dead code. To make it work, devices without +;; SP_H must get their own multilib(s). + clr r29 +#else in r29, __SP_H__ +#endif /* #SP = 8/16 */ ldi r30, 12 XJMP __epilogue_restores__ + ((18 - 12) * 2) @@ -1229,6 +1236,15 @@ DEFUN __prologue_saves__ push r17 push r28 push r29 +#if defined (__AVR_HAVE_8BIT_SP__) +;; FIXME: __AVR_HAVE_8BIT_SP__ is set on device level, not on core level +;; so this lines are dead code. To make it work, devices without +;; SP_H must get their own multilib(s). + in r28,__SP_L__ + sub r28,r26 + out __SP_L__,r28 + clr r29 +#else in r28,__SP_L__ in r29,__SP_H__ sub r28,r26 @@ -1238,6 +1254,8 @@ DEFUN __prologue_saves__ out __SP_H__,r29 out __SREG__,__tmp_reg__ out __SP_L__,r28 +#endif /* #SP = 8/16 */ + #if defined (__AVR_HAVE_EIJMP_EICALL__) eijmp #else @@ -1270,6 +1288,15 @@ DEFUN __epilogue_restores__ ldd r16,Y+4 ldd r17,Y+3 ldd r26,Y+2 +#if defined (__AVR_HAVE_8BIT_SP__) +;; FIXME: __AVR_HAVE_8BIT_SP__ is set on device level, not on core level +;; so this lines are dead code. To make it work, devices without +;; SP_H must get their own multilib(s). + ldd r29,Y+1 + add r28,r30 + out __SP_L__,r28 + mov r28, r26 +#else ldd r27,Y+1 add r28,r30 adc r29,__zero_reg__ @@ -1280,6 +1307,7 @@ DEFUN __epilogue_restores__ out __SP_L__,r28 mov_l r28, r26 mov_h r29, r27 +#endif /* #SP = 8/16 */ ret ENDF __epilogue_restores__ #endif /* defined (L_epilogue) */