From: Craig Topper <craig.topper@gmail.com>
Date: Thu, 24 Nov 2016 21:48:52 +0000 (+0000)
Subject: [DAGCombine] Teach DAG combine that if both inputs of a vselect are the same, then... 
X-Git-Tag: llvmorg-4.0.0-rc1~3690
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8c4cdf06db3e2261ff6db220273ecfc09b6c23a7;p=platform%2Fupstream%2Fllvm.git

[DAGCombine] Teach DAG combine that if both inputs of a vselect are the same, then the condition doesn't matter and the vselect can be removed.

Selects with scalar condition already handle this correctly.

llvm-svn: 287904
---

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e3cab19..49e6490 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5774,6 +5774,10 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
   SDValue N2 = N->getOperand(2);
   SDLoc DL(N);
 
+  // fold (vselect C, X, X) -> X
+  if (N1 == N2)
+    return N1;
+
   // Canonicalize integer abs.
   // vselect (setg[te] X,  0),  X, -X ->
   // vselect (setgt    X, -1),  X, -X ->