From: Yangyu Chen <cyy@cyyself.name>
Date: Tue, 30 Jul 2024 00:28:05 +0000 (+0000)
Subject: dt-bindings: riscv: Add SpacemiT X60 compatibles
X-Git-Tag: accepted/tizen/unified/x/20240911.015644~51
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8c170c045e1fa5813766d286359da446bf02da0d;p=platform%2Fkernel%2Flinux-riscv.git

dt-bindings: riscv: Add SpacemiT X60 compatibles

The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
SoC.

Link: https://www.spacemit.com/en/spacemit-x60-core/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
[ m.wilczynski: ported from
https://lore.kernel.org/all/20240730-k1-01-basic-dt-v5-0-98263aae83be@gentoo.org/
]
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>

Change-Id: I1c61cf1f65e5f34b0be2639669ec11f33991610c
---

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..7fe29a2a082f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -45,6 +45,7 @@ properties:
               - sifive,u7
               - sifive,u74
               - sifive,u74-mc
+              - spacemit,x60
               - thead,c906
               - thead,c910
           - const: riscv