From: Francisco Jerez Date: Fri, 2 Sep 2016 05:12:04 +0000 (-0700) Subject: i965/vec4: Assign correct destination offset to rewritten instruction in register... X-Git-Tag: upstream/17.1.0~6321 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8bed1adfc144d9ae8d55ccb9b277942da8a78064;p=platform%2Fupstream%2Fmesa.git i965/vec4: Assign correct destination offset to rewritten instruction in register coalesce. Because the pass already checks that the destination offset of each 'scan_inst' that needs to be rewritten matches 'inst->src[0].offset' exactly, the final offset of the rewritten instruction is just the original destination offset of the copy. This is in preparation for adding support for sub-GRF offsets to the VEC4 IR. Reviewed-by: Iago Toral Quiroga --- diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 8f8d262..470f814 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -1254,8 +1254,7 @@ vec4_visitor::opt_register_coalesce() inst->src[0].swizzle); scan_inst->dst.file = inst->dst.file; scan_inst->dst.nr = inst->dst.nr; - scan_inst->dst.offset = scan_inst->dst.offset % REG_SIZE + - ROUND_DOWN_TO(inst->dst.offset, REG_SIZE); + scan_inst->dst.offset = inst->dst.offset; if (inst->saturate && inst->dst.type != scan_inst->dst.type) { /* If we have reached this point, scan_inst is a non