From: Andrew Cagney <cagney@redhat.com>
Date: Wed, 17 Sep 1997 13:46:29 +0000 (+0000)
Subject: Test US bit of v850eq.
X-Git-Tag: gdb-4_18~4710
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8bd89725a7dfd1c709791f2d472a8cd8d35612dc;p=external%2Fbinutils.git

Test US bit of v850eq.
Loop program for testing interrupt delivery.
---

diff --git a/sim/testsuite/v850eq-elf/Makefile.in b/sim/testsuite/v850eq-elf/Makefile.in
index 567f291..7f4c969 100644
--- a/sim/testsuite/v850eq-elf/Makefile.in
+++ b/sim/testsuite/v850eq-elf/Makefile.in
@@ -89,6 +89,7 @@ TESTS= \
 	t-ctret.ok \
 	t-hsw.ok \
 	t-ldsr.ok \
+	t-sld.ok \
 	t-sxb.ok \
 	t-sxh.ok \
 	t-zxb.ok \
diff --git a/sim/testsuite/v850eq-elf/loop.s b/sim/testsuite/v850eq-elf/loop.s
new file mode 100644
index 0000000..bdd870b
--- /dev/null
+++ b/sim/testsuite/v850eq-elf/loop.s
@@ -0,0 +1,7 @@
+.include "t-macros.i"
+
+	start
+
+loop:	br loop
+
+	exit0
diff --git a/sim/testsuite/v850eq-elf/t-sld.s b/sim/testsuite/v850eq-elf/t-sld.s
new file mode 100644
index 0000000..861a9bf
--- /dev/null
+++ b/sim/testsuite/v850eq-elf/t-sld.s
@@ -0,0 +1,57 @@
+.include "t-macros.i"
+
+	start
+
+	# ensure that the US bit is clear
+	load r2 0xff
+	stsr psw, r3
+	and r2, r3
+	ldsr r3, psw
+
+	# put something into EP
+	load ep ep_base
+	
+test_sldb1:
+	sld.b 0[ep], r4
+	check1 r4 0xffffff80
+	
+test_sldbu1:
+	sld.bu 0[ep], r4
+	check1 r4, 0x80
+
+test_sldh1:
+	sld.h 0[ep], r4
+	check1 r4 0xffff8080
+	
+test_sldhu1:
+	sld.hu 0[ep], r4
+	check1 r4, 0x8080
+
+	
+	# Now set the US bit
+	load r2 0x100
+	stsr psw, r3
+	or r2, r3
+	ldsr r3, psw
+
+	
+test_sldb2:
+	sld.b 0[ep], r4
+	check1 r4, 0x80
+	
+test_sldbu2:
+	sld.bu 0[ep], r4
+	check1 r4 0xffffff80
+
+test_sldh2:
+	sld.h 0[ep], r4
+	check1 r4, 0x8080
+	
+test_sldhu2:
+	sld.hu 0[ep], r4
+	check1 r4 0xffff8080
+
+	exit0
+
+ep_base:
+	.short 0x8080