From: Vineet Gupta Date: Thu, 2 Feb 2017 17:09:50 +0000 (-0800) Subject: ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant X-Git-Tag: v4.14-rc1~1460^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8ba605b607b7278548c1092b2ac36381627f0839;p=platform%2Fkernel%2Flinux-rpi.git ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant A typical SMP system expects cache coherency. Initial NPS platform support was slated to be SMP w/o cache coherency. However it seems the platform now selects that option, so there is no point in keeping it around. Signed-off-by: Vineet Gupta --- diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index ba15cb8..c9f30f4 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -180,16 +180,12 @@ config CPU_BIG_ENDIAN config SMP bool "Symmetric Multi-Processing" default n - select ARC_HAS_COH_CACHES if ISA_ARCV2 select ARC_MCIP if ISA_ARCV2 help This enables support for systems with more than one CPU. if SMP -config ARC_HAS_COH_CACHES - def_bool n - config NR_CPUS int "Maximum number of CPUs (2-4096)" range 2 4096 @@ -219,8 +215,6 @@ config ARC_MCIP menuconfig ARC_CACHE bool "Enable Cache Support" default y - # if SMP, cache enabled ONLY if ARC implementation has cache coherency - depends on !SMP || ARC_HAS_COH_CACHES if ARC_CACHE diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig index 1d175cc..1595a38 100644 --- a/arch/arc/plat-eznps/Kconfig +++ b/arch/arc/plat-eznps/Kconfig @@ -5,7 +5,6 @@ menuconfig ARC_PLAT_EZNPS bool "\"EZchip\" ARC dev platform" - select ARC_HAS_COH_CACHES if SMP select CPU_BIG_ENDIAN select CLKSRC_NPS select EZNPS_GIC diff --git a/arch/arc/plat-sim/Kconfig b/arch/arc/plat-sim/Kconfig index 18e39fc..ac6af96 100644 --- a/arch/arc/plat-sim/Kconfig +++ b/arch/arc/plat-sim/Kconfig @@ -8,7 +8,6 @@ menuconfig ARC_PLAT_SIM bool "ARC nSIM based simulation virtual platforms" - select ARC_HAS_COH_CACHES if SMP help Support for nSIM based ARC simulation platforms This includes the standalone nSIM (uart only) vs. System C OSCI VP