From: Sander de Smalen Date: Thu, 2 Jul 2020 13:40:08 +0000 (+0100) Subject: [AArch64][SVE] NFC: Rename isOrig -> isReverseInstr X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8b7b0ad24c7323c629a76bb04305c698745be568;p=platform%2Fupstream%2Fllvm.git [AArch64][SVE] NFC: Rename isOrig -> isReverseInstr This is a non-functional to clarify some of the terminology in the AArch64SVEInstrInfo/SVEInstrFormats.td files around the tables for mapping an instruction to it's reverse instruction counter part, and vice versa. e.g. DIV -> DIVR and DIVR -> DIV. Reviewers: paulwalker-arm, cameron.mcinally, rengolin, efriedma Reviewed By: paulwalker-arm, efriedma Tags: #llvm Differential Revision: https://reviews.llvm.org/D82979 --- diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index b903486..2058764 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -444,10 +444,13 @@ bool AArch64ExpandPseudo::expand_DestructiveOp( // Resolve the reverse opcode if (UseRev) { - if (AArch64::getSVERevInstr(Opcode) != -1) - Opcode = AArch64::getSVERevInstr(Opcode); - else if (AArch64::getSVEOrigInstr(Opcode) != -1) - Opcode = AArch64::getSVEOrigInstr(Opcode); + int NewOpcode; + // e.g. DIV -> DIVR + if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1) + Opcode = NewOpcode; + // e.g. DIVR -> DIV + else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1) + Opcode = NewOpcode; } // Get the right MOVPRFX diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index c71e345..298c04d 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -442,7 +442,7 @@ enum FalseLaneType { int getSVEPseudoMap(uint16_t Opcode); int getSVERevInstr(uint16_t Opcode); -int getSVEOrigInstr(uint16_t Opcode); +int getSVENonRevInstr(uint16_t Opcode); } } // end namespace llvm diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index c7a6060e..8250822 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -221,8 +221,8 @@ let Predicates = [HasSVE] in { defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic", null_frag>; defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", "ADD_ZPZZ", int_aarch64_sve_add, DestructiveBinaryComm>; - defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub", "SUB_ZPZZ", int_aarch64_sve_sub, DestructiveBinaryCommWithRev, "SUBR_ZPmZ", 1>; - defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr", "SUBR_ZPZZ", int_aarch64_sve_subr, DestructiveBinaryCommWithRev, "SUB_ZPmZ", 0>; + defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub", "SUB_ZPZZ", int_aarch64_sve_sub, DestructiveBinaryCommWithRev, "SUBR_ZPmZ">; + defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr", "SUBR_ZPZZ", int_aarch64_sve_subr, DestructiveBinaryCommWithRev, "SUB_ZPmZ", /*isReverseInstr*/ 1>; defm ADD_ZPZZ : sve_int_bin_pred_bhsd; @@ -285,10 +285,10 @@ let Predicates = [HasSVE] in { def : Pat<(mul nxv2i64:$Op1, nxv2i64:$Op2), (MUL_ZPmZ_D (PTRUE_D 31), $Op1, $Op2)>; - defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv", "SDIV_ZPZZ", int_aarch64_sve_sdiv, DestructiveBinaryCommWithRev, "SDIVR_ZPmZ", 1>; - defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv", "UDIV_ZPZZ", int_aarch64_sve_udiv, DestructiveBinaryCommWithRev, "UDIVR_ZPmZ", 1>; - defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr", "SDIVR_ZPZZ", int_aarch64_sve_sdivr, DestructiveBinaryCommWithRev, "SDIV_ZPmZ", 0>; - defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr", "UDIVR_ZPZZ", int_aarch64_sve_udivr, DestructiveBinaryCommWithRev, "UDIV_ZPmZ", 0>; + defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv", "SDIV_ZPZZ", int_aarch64_sve_sdiv, DestructiveBinaryCommWithRev, "SDIVR_ZPmZ">; + defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv", "UDIV_ZPZZ", int_aarch64_sve_udiv, DestructiveBinaryCommWithRev, "UDIVR_ZPmZ">; + defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr", "SDIVR_ZPZZ", int_aarch64_sve_sdivr, DestructiveBinaryCommWithRev, "SDIV_ZPmZ", /*isReverseInstr*/ 1>; + defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr", "UDIVR_ZPZZ", int_aarch64_sve_udivr, DestructiveBinaryCommWithRev, "UDIV_ZPmZ", /*isReverseInstr*/ 1>; defm SDIV_ZPZZ : sve_int_bin_pred_sd; defm UDIV_ZPZZ : sve_int_bin_pred_sd; @@ -341,9 +341,9 @@ let Predicates = [HasSVE] in { defm FMIN_ZPmI : sve_fp_2op_i_p_zds<0b111, "fmin", sve_fpimm_zero_one>; defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd", "FADD_ZPZZ", int_aarch64_sve_fadd, DestructiveBinaryComm>; - defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub", "FSUB_ZPZZ", int_aarch64_sve_fsub, DestructiveBinaryCommWithRev, "FSUBR_ZPmZ", 1>; + defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub", "FSUB_ZPZZ", int_aarch64_sve_fsub, DestructiveBinaryCommWithRev, "FSUBR_ZPmZ">; defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul", "FMUL_ZPZZ", int_aarch64_sve_fmul, DestructiveBinaryComm>; - defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr", "FSUBR_ZPZZ", int_aarch64_sve_fsubr, DestructiveBinaryCommWithRev, "FSUB_ZPmZ", 0>; + defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr", "FSUBR_ZPZZ", int_aarch64_sve_fsubr, DestructiveBinaryCommWithRev, "FSUB_ZPmZ", /*isReverseInstr*/ 1>; defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm", "FMAXNM_ZPZZ", int_aarch64_sve_fmaxnm, DestructiveBinaryComm>; defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm", "FMINNM_ZPZZ", int_aarch64_sve_fminnm, DestructiveBinaryComm>; defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax", "FMAX_ZPZZ", int_aarch64_sve_fmax, DestructiveBinaryComm>; @@ -351,8 +351,8 @@ let Predicates = [HasSVE] in { defm FABD_ZPmZ : sve_fp_2op_p_zds<0b1000, "fabd", "FABD_ZPZZ", int_aarch64_sve_fabd, DestructiveBinaryComm>; defm FSCALE_ZPmZ : sve_fp_2op_p_zds_fscale<0b1001, "fscale", int_aarch64_sve_fscale>; defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx", "FMULX_ZPZZ", int_aarch64_sve_fmulx, DestructiveBinaryComm>; - defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr", "FDIVR_ZPZZ", int_aarch64_sve_fdivr, DestructiveBinaryCommWithRev, "FDIV_ZPmZ", 0>; - defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv", "FDIV_ZPZZ", int_aarch64_sve_fdiv, DestructiveBinaryCommWithRev, "FDIVR_ZPmZ", 1>; + defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr", "FDIVR_ZPZZ", int_aarch64_sve_fdivr, DestructiveBinaryCommWithRev, "FDIV_ZPmZ", /*isReverseInstr*/ 1>; + defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv", "FDIV_ZPZZ", int_aarch64_sve_fdiv, DestructiveBinaryCommWithRev, "FDIVR_ZPmZ">; defm FADD_ZPZZ : sve_fp_bin_pred_hfd; @@ -1271,12 +1271,12 @@ multiclass sve_prefetch; } - defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr", "ASR_ZPZZ", AArch64asr_m1, "ASRR_ZPmZ", 1>; - defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr", "LSR_ZPZZ", AArch64lsr_m1, "LSRR_ZPmZ", 1>; - defm LSL_ZPmZ : sve_int_bin_pred_shift<0b011, "lsl", "LSL_ZPZZ", AArch64lsl_m1, "LSLR_ZPmZ", 1>; - defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr", "ASRR_ZPZZ", null_frag, "ASR_ZPmZ", 0>; - defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr", "LSRR_ZPZZ", null_frag, "LSR_ZPmZ", 0>; - defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr", "LSLR_ZPZZ", null_frag, "LSL_ZPmZ", 0>; + defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr", "ASR_ZPZZ", AArch64asr_m1, "ASRR_ZPmZ">; + defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr", "LSR_ZPZZ", AArch64lsr_m1, "LSRR_ZPmZ">; + defm LSL_ZPmZ : sve_int_bin_pred_shift<0b011, "lsl", "LSL_ZPZZ", AArch64lsl_m1, "LSLR_ZPmZ">; + defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr", "ASRR_ZPZZ", null_frag, "ASR_ZPmZ", /*isReverseInstr*/ 1>; + defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr", "LSRR_ZPZZ", null_frag, "LSR_ZPmZ", /*isReverseInstr*/ 1>; + defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr", "LSLR_ZPZZ", null_frag, "LSL_ZPmZ", /*isReverseInstr*/ 1>; defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr", int_aarch64_sve_asr_wide>; defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr", int_aarch64_sve_lsr_wide>; @@ -2288,13 +2288,6 @@ let Predicates = [HasSVE2] in { defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr", null_frag>; defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr", null_frag>; - // SVE2 predicated shifts - defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl", "SQSHL_ZPZI">; - defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl", "UQSHL_ZPZI">; - defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr", "SRSHR_ZPZI", int_aarch64_sve_srshr>; - defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr", "URSHR_ZPZI", int_aarch64_sve_urshr>; - defm SQSHLU_ZPmI : sve2_int_bin_pred_shift_imm_left< 0b1111, "sqshlu", "SQSHLU_ZPZI", int_aarch64_sve_sqshlu>; - let Predicates = [HasSVE2, UseExperimentalZeroingPseudos] in { defm SQSHL_ZPZI : sve_int_bin_pred_shift_imm_left_zeroing_bhsd; defm UQSHL_ZPZI : sve_int_bin_pred_shift_imm_left_zeroing_bhsd; @@ -2303,6 +2296,13 @@ let Predicates = [HasSVE2] in { defm SQSHLU_ZPZI : sve_int_bin_pred_shift_imm_left_zeroing_bhsd; } + // SVE2 predicated shifts + defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl", "SQSHL_ZPZI">; + defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl", "UQSHL_ZPZI">; + defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr", "SRSHR_ZPZI", int_aarch64_sve_srshr>; + defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr", "URSHR_ZPZI", int_aarch64_sve_urshr>; + defm SQSHLU_ZPmI : sve2_int_bin_pred_shift_imm_left< 0b1111, "sqshlu", "SQSHLU_ZPZI", int_aarch64_sve_sqshlu>; + // SVE2 integer add/subtract long defm SADDLB_ZZZ : sve2_wide_int_arith_long<0b00000, "saddlb", int_aarch64_sve_saddlb>; defm SADDLT_ZZZ : sve2_wide_int_arith_long<0b00001, "saddlt", int_aarch64_sve_saddlt>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 26d3765..a005d1e 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -419,25 +419,27 @@ class SVEPseudo2Instr { bit IsInstr = instr; } +// Lookup e.g. DIV -> DIVR def getSVERevInstr : InstrMapping { let FilterClass = "SVEInstr2Rev"; let RowFields = ["InstrName"]; - let ColFields = ["IsOrig"]; - let KeyCol = ["1"]; - let ValueCols = [["0"]]; + let ColFields = ["isReverseInstr"]; + let KeyCol = ["0"]; + let ValueCols = [["1"]]; } -def getSVEOrigInstr : InstrMapping { +// Lookup e.g. DIVR -> DIV +def getSVENonRevInstr : InstrMapping { let FilterClass = "SVEInstr2Rev"; let RowFields = ["InstrName"]; - let ColFields = ["IsOrig"]; - let KeyCol = ["0"]; - let ValueCols = [["1"]]; + let ColFields = ["isReverseInstr"]; + let KeyCol = ["1"]; + let ValueCols = [["0"]]; } -class SVEInstr2Rev { - string InstrName = !if(nameIsOrig, name, revname); - bit IsOrig = nameIsOrig; +class SVEInstr2Rev { + string InstrName = !if(name1IsReverseInstr, name1, name2); + bit isReverseInstr = name1IsReverseInstr; } // @@ -1570,14 +1572,14 @@ class sve_fp_2op_p_zds sz, bits<4> opc, string asm, multiclass sve_fp_2op_p_zds opc, string asm, string Ps, SDPatternOperator op, DestructiveInstTypeEnum flags, - string revname="", bit isOrig=0> { + string revname="", bit isReverseInstr=0> { let DestructiveInstType = flags in { def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; } def : SVE_3_Op_Pat(NAME # _H)>; @@ -2352,16 +2354,16 @@ multiclass sve_int_bin_pred_log opc, string asm, SDPatternOperator op> { multiclass sve_int_bin_pred_arit_0 opc, string asm, string Ps, SDPatternOperator op, DestructiveInstTypeEnum flags, - string revname="", bit isOrig=0> { + string revname="", bit isReverseInstr=0> { let DestructiveInstType = flags in { def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; } def : SVE_3_Op_Pat(NAME # _B)>; @@ -2398,12 +2400,12 @@ multiclass sve_int_bin_pred_arit_2 opc, string asm, SDPatternOperator op multiclass sve_int_bin_pred_arit_2_div opc, string asm, string Ps, SDPatternOperator op, DestructiveInstTypeEnum flags, - string revname="", bit isOrig=0> { + string revname="", bit isReverseInstr=0> { let DestructiveInstType = flags in { def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; } def : SVE_3_Op_Pat(NAME # _S)>; @@ -4843,16 +4845,16 @@ class sve_int_bin_pred_shift sz8_64, bit wide, bits<3> opc, } multiclass sve_int_bin_pred_shift opc, string asm, string Ps, - SDPatternOperator op, string revname, bit isOrig> { + SDPatternOperator op, string revname, bit isReverseInstr = 0> { let DestructiveInstType = DestructiveBinaryCommWithRev in { def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>, - SVEPseudo2Instr, SVEInstr2Rev; + SVEPseudo2Instr, SVEInstr2Rev; } def : SVE_3_Op_Pat(NAME # _B)>; def : SVE_3_Op_Pat(NAME # _H)>;