From: Matt Arsenault Date: Thu, 18 May 2023 08:22:54 +0000 (+0100) Subject: Revert "AMDGPU: Add baseline test for f16 fmed3 matching" X-Git-Tag: upstream/17.0.6~8035 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8b321a25e1d87327840b8305264380e8de47c4ea;p=platform%2Fupstream%2Fllvm.git Revert "AMDGPU: Add baseline test for f16 fmed3 matching" This reverts commit b233eb70cd82ca3c320fac4bb8c2cccd1fe97696. --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.f16.ll deleted file mode 100644 index 8d0e2ba..0000000 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.f16.ll +++ /dev/null @@ -1,1236 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s -; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s - -define amdgpu_kernel void @v_test_global_nnans_med3_f16_pat0_srcmod0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #2 { -; SI-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod0: -; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 -; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: s_mov_b32 s10, 0 -; SI-NEXT: s_mov_b32 s11, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[2:3] -; SI-NEXT: buffer_load_ushort v2, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[4:5] -; SI-NEXT: buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[6:7] -; SI-NEXT: buffer_load_ushort v4, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e64 v2, -v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 -; SI-NEXT: v_min_f32_e32 v5, v2, v3 -; SI-NEXT: v_max_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_min_f32_e32 v2, v2, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_max_f32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: s_mov_b64 s[2:3], s[10:11] -; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 -; SI-NEXT: s_endpgm -; -; VI-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod0: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; VI-NEXT: v_lshlrev_b32_e32 v6, 1, v0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v2, s4 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_mov_b32_e32 v5, s7 -; VI-NEXT: flat_load_ushort v7, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v2, v[2:3] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_add_u32_e32 v0, vcc, v4, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; VI-NEXT: flat_load_ushort v3, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_max_f16_e64 v4, -v7, -v7 -; VI-NEXT: v_min_f16_e32 v5, v4, v2 -; VI-NEXT: v_max_f16_e32 v2, v4, v2 -; VI-NEXT: v_min_f16_e32 v2, v2, v3 -; VI-NEXT: v_max_f16_e32 v2, v5, v2 -; VI-NEXT: flat_store_short v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX9-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX9-NEXT: global_store_short v0, v1, s[0:1] -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX10-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX10-NEXT: global_store_short v0, v1, s[0:1] -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v3, v0, s[6:7] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid - %gep1 = getelementptr half, ptr addrspace(1) %bptr, i32 %tid - %gep2 = getelementptr half, ptr addrspace(1) %cptr, i32 %tid - %outgep = getelementptr half, ptr addrspace(1) %out, i32 %tid - %a = load volatile half, ptr addrspace(1) %gep0 - %b = load volatile half, ptr addrspace(1) %gep1 - %c = load volatile half, ptr addrspace(1) %gep2 - %a.fneg = fsub half -0.0, %a - %tmp0 = call half @llvm.minnum.f16(half %a.fneg, half %b) - %tmp1 = call half @llvm.maxnum.f16(half %a.fneg, half %b) - %tmp2 = call half @llvm.minnum.f16(half %tmp1, half %c) - %med3 = call half @llvm.maxnum.f16(half %tmp0, half %tmp2) - store half %med3, ptr addrspace(1) %outgep - ret void -} - -define amdgpu_kernel void @v_test_global_nnans_med3_f16_pat1_srcmod0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #2 { -; SI-LABEL: v_test_global_nnans_med3_f16_pat1_srcmod0: -; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 -; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: s_mov_b32 s10, 0 -; SI-NEXT: s_mov_b32 s11, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[2:3] -; SI-NEXT: buffer_load_ushort v2, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[4:5] -; SI-NEXT: buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[6:7] -; SI-NEXT: buffer_load_ushort v4, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e64 v2, -v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 -; SI-NEXT: v_max_f32_e32 v5, v2, v3 -; SI-NEXT: v_min_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_max_f32_e32 v2, v2, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_min_f32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: s_mov_b64 s[2:3], s[10:11] -; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 -; SI-NEXT: s_endpgm -; -; VI-LABEL: v_test_global_nnans_med3_f16_pat1_srcmod0: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; VI-NEXT: v_lshlrev_b32_e32 v6, 1, v0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v2, s4 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_mov_b32_e32 v5, s7 -; VI-NEXT: flat_load_ushort v7, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v2, v[2:3] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_add_u32_e32 v0, vcc, v4, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; VI-NEXT: flat_load_ushort v3, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_max_f16_e64 v4, -v7, -v7 -; VI-NEXT: v_max_f16_e32 v5, v4, v2 -; VI-NEXT: v_min_f16_e32 v2, v4, v2 -; VI-NEXT: v_max_f16_e32 v2, v2, v3 -; VI-NEXT: v_min_f16_e32 v2, v5, v2 -; VI-NEXT: flat_store_short v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_test_global_nnans_med3_f16_pat1_srcmod0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX9-NEXT: v_max_f16_e32 v4, v1, v2 -; GFX9-NEXT: v_min_f16_e32 v1, v1, v2 -; GFX9-NEXT: v_max_f16_e32 v1, v1, v3 -; GFX9-NEXT: v_min_f16_e32 v1, v4, v1 -; GFX9-NEXT: global_store_short v0, v1, s[0:1] -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: v_test_global_nnans_med3_f16_pat1_srcmod0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX10-NEXT: v_min_f16_e32 v4, v1, v2 -; GFX10-NEXT: v_max_f16_e32 v1, v1, v2 -; GFX10-NEXT: v_max_f16_e32 v2, v4, v3 -; GFX10-NEXT: v_min_f16_e32 v1, v1, v2 -; GFX10-NEXT: global_store_short v0, v1, s[0:1] -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: v_test_global_nnans_med3_f16_pat1_srcmod0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v3, v0, s[6:7] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_max_f16_e32 v4, v1, v2 -; GFX11-NEXT: v_min_f16_e32 v1, v1, v2 -; GFX11-NEXT: v_maxmin_f16 v1, v1, v3, v4 -; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid - %gep1 = getelementptr half, ptr addrspace(1) %bptr, i32 %tid - %gep2 = getelementptr half, ptr addrspace(1) %cptr, i32 %tid - %outgep = getelementptr half, ptr addrspace(1) %out, i32 %tid - %a = load volatile half, ptr addrspace(1) %gep0 - %b = load volatile half, ptr addrspace(1) %gep1 - %c = load volatile half, ptr addrspace(1) %gep2 - %a.fneg = fsub half -0.0, %a - %tmp0 = call half @llvm.maxnum.f16(half %a.fneg, half %b) - %tmp1 = call half @llvm.minnum.f16(half %a.fneg, half %b) - %tmp2 = call half @llvm.maxnum.f16(half %tmp1, half %c) - %med3 = call half @llvm.minnum.f16(half %tmp0, half %tmp2) - store half %med3, ptr addrspace(1) %outgep - ret void -} - -define amdgpu_kernel void @v_test_no_global_nnans_med3_f16_pat0_srcmod0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #1 { -; SI-LABEL: v_test_no_global_nnans_med3_f16_pat0_srcmod0: -; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 -; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: s_mov_b32 s10, 0 -; SI-NEXT: s_mov_b32 s11, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[2:3] -; SI-NEXT: buffer_load_ushort v2, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[4:5] -; SI-NEXT: buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[6:7] -; SI-NEXT: buffer_load_ushort v4, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e64 v2, -v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 -; SI-NEXT: v_min_f32_e32 v5, v2, v3 -; SI-NEXT: v_max_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_min_f32_e32 v2, v2, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_max_f32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: s_mov_b64 s[2:3], s[10:11] -; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 -; SI-NEXT: s_endpgm -; -; VI-LABEL: v_test_no_global_nnans_med3_f16_pat0_srcmod0: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; VI-NEXT: v_lshlrev_b32_e32 v6, 1, v0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v2, s4 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_mov_b32_e32 v5, s7 -; VI-NEXT: flat_load_ushort v7, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v2, v[2:3] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_add_u32_e32 v0, vcc, v4, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; VI-NEXT: flat_load_ushort v3, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_max_f16_e64 v4, -v7, -v7 -; VI-NEXT: v_max_f16_e32 v2, v2, v2 -; VI-NEXT: v_min_f16_e32 v5, v4, v2 -; VI-NEXT: v_max_f16_e32 v2, v4, v2 -; VI-NEXT: v_max_f16_e32 v3, v3, v3 -; VI-NEXT: v_min_f16_e32 v2, v2, v3 -; VI-NEXT: v_max_f16_e32 v2, v5, v2 -; VI-NEXT: flat_store_short v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_test_no_global_nnans_med3_f16_pat0_srcmod0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX9-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX9-NEXT: v_min_f16_e32 v4, v1, v2 -; GFX9-NEXT: v_max_f16_e32 v1, v1, v2 -; GFX9-NEXT: v_max_f16_e32 v2, v3, v3 -; GFX9-NEXT: v_min_f16_e32 v1, v1, v2 -; GFX9-NEXT: v_max_f16_e32 v1, v4, v1 -; GFX9-NEXT: global_store_short v0, v1, s[0:1] -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: v_test_no_global_nnans_med3_f16_pat0_srcmod0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX10-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX10-NEXT: v_max_f16_e32 v3, v3, v3 -; GFX10-NEXT: v_max_f16_e32 v4, v1, v2 -; GFX10-NEXT: v_min_f16_e32 v1, v1, v2 -; GFX10-NEXT: v_min_f16_e32 v2, v4, v3 -; GFX10-NEXT: v_max_f16_e32 v1, v1, v2 -; GFX10-NEXT: global_store_short v0, v1, s[0:1] -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: v_test_no_global_nnans_med3_f16_pat0_srcmod0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v3, v0, s[6:7] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX11-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_min_f16_e32 v4, v1, v2 -; GFX11-NEXT: v_max_f16_e32 v1, v1, v2 -; GFX11-NEXT: v_max_f16_e32 v2, v3, v3 -; GFX11-NEXT: v_minmax_f16 v1, v1, v2, v4 -; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid - %gep1 = getelementptr half, ptr addrspace(1) %bptr, i32 %tid - %gep2 = getelementptr half, ptr addrspace(1) %cptr, i32 %tid - %outgep = getelementptr half, ptr addrspace(1) %out, i32 %tid - %a = load volatile half, ptr addrspace(1) %gep0 - %b = load volatile half, ptr addrspace(1) %gep1 - %c = load volatile half, ptr addrspace(1) %gep2 - %a.fneg = fsub half -0.0, %a - %tmp0 = call half @llvm.minnum.f16(half %a.fneg, half %b) - %tmp1 = call half @llvm.maxnum.f16(half %a.fneg, half %b) - %tmp2 = call half @llvm.minnum.f16(half %tmp1, half %c) - %med3 = call half @llvm.maxnum.f16(half %tmp0, half %tmp2) - store half %med3, ptr addrspace(1) %outgep - ret void -} - -define amdgpu_kernel void @v_test_nnan_on_call_med3_f16_pat0_srcmod0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #1 { -; SI-LABEL: v_test_nnan_on_call_med3_f16_pat0_srcmod0: -; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 -; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: s_mov_b32 s10, 0 -; SI-NEXT: s_mov_b32 s11, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[2:3] -; SI-NEXT: buffer_load_ushort v2, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[4:5] -; SI-NEXT: buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[6:7] -; SI-NEXT: buffer_load_ushort v4, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e64 v2, -v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 -; SI-NEXT: v_min_f32_e32 v5, v2, v3 -; SI-NEXT: v_max_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_min_f32_e32 v2, v2, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_max_f32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: s_mov_b64 s[2:3], s[10:11] -; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 -; SI-NEXT: s_endpgm -; -; VI-LABEL: v_test_nnan_on_call_med3_f16_pat0_srcmod0: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; VI-NEXT: v_lshlrev_b32_e32 v6, 1, v0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v2, s4 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_mov_b32_e32 v5, s7 -; VI-NEXT: flat_load_ushort v7, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v2, v[2:3] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_add_u32_e32 v0, vcc, v4, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc -; VI-NEXT: flat_load_ushort v3, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_max_f16_e64 v4, -v7, -v7 -; VI-NEXT: v_min_f16_e32 v5, v4, v2 -; VI-NEXT: v_max_f16_e32 v2, v4, v2 -; VI-NEXT: v_min_f16_e32 v2, v2, v3 -; VI-NEXT: v_max_f16_e32 v2, v5, v2 -; VI-NEXT: flat_store_short v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_test_nnan_on_call_med3_f16_pat0_srcmod0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX9-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX9-NEXT: global_store_short v0, v1, s[0:1] -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: v_test_nnan_on_call_med3_f16_pat0_srcmod0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX10-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX10-NEXT: global_store_short v0, v1, s[0:1] -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: v_test_nnan_on_call_med3_f16_pat0_srcmod0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v3, v0, s[6:7] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid - %gep1 = getelementptr half, ptr addrspace(1) %bptr, i32 %tid - %gep2 = getelementptr half, ptr addrspace(1) %cptr, i32 %tid - %outgep = getelementptr half, ptr addrspace(1) %out, i32 %tid - %a = load volatile half, ptr addrspace(1) %gep0 - %b = load volatile half, ptr addrspace(1) %gep1 - %c = load volatile half, ptr addrspace(1) %gep2 - %a.fneg = fsub half -0.0, %a - %tmp0 = call nnan half @llvm.minnum.f16(half %a.fneg, half %b) - %tmp1 = call nnan half @llvm.maxnum.f16(half %a.fneg, half %b) - %tmp2 = call nnan half @llvm.minnum.f16(half %tmp1, half %c) - %med3 = call nnan half @llvm.maxnum.f16(half %tmp0, half %tmp2) - store half %med3, ptr addrspace(1) %outgep - ret void -} - -define amdgpu_kernel void @v_test_global_nnans_med3_f16_pat0_srcmod012(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #2 { -; SI-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod012: -; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 -; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: s_mov_b32 s10, 0 -; SI-NEXT: s_mov_b32 s11, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[2:3] -; SI-NEXT: buffer_load_ushort v2, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[4:5] -; SI-NEXT: buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[6:7] -; SI-NEXT: buffer_load_ushort v4, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e64 v2, -v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e64 v3, |v3| -; SI-NEXT: v_cvt_f32_f16_e64 v4, -|v4| -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 -; SI-NEXT: v_min_f32_e32 v5, v2, v3 -; SI-NEXT: v_max_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_min_f32_e32 v2, v2, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_max_f32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: s_mov_b64 s[2:3], s[10:11] -; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 -; SI-NEXT: s_endpgm -; -; VI-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod012: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; VI-NEXT: v_lshlrev_b32_e32 v6, 1, v0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v2, s4 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_mov_b32_e32 v5, s7 -; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 -; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; VI-NEXT: flat_load_ushort v7, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v2, v[2:3] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v3, v[4:5] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_max_f16_e64 v4, -v7, -v7 -; VI-NEXT: v_min_f16_e64 v5, v4, |v2| -; VI-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| -; VI-NEXT: v_max_f16_e64 v2, v4, |v2| -; VI-NEXT: v_min_f16_e32 v2, v2, v3 -; VI-NEXT: v_max_f16_e32 v2, v5, v2 -; VI-NEXT: flat_store_short v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod012: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX9-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| -; GFX9-NEXT: v_med3_f16 v1, v1, |v2|, v3 -; GFX9-NEXT: global_store_short v0, v1, s[0:1] -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod012: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX10-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| -; GFX10-NEXT: v_med3_f16 v1, v1, |v2|, v3 -; GFX10-NEXT: global_store_short v0, v1, s[0:1] -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: v_test_global_nnans_med3_f16_pat0_srcmod012: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v3, v0, s[6:7] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_max_f16_e64 v1, -v1, -v1 -; GFX11-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_med3_f16 v1, v1, |v2|, v3 -; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid - %gep1 = getelementptr half, ptr addrspace(1) %bptr, i32 %tid - %gep2 = getelementptr half, ptr addrspace(1) %cptr, i32 %tid - %outgep = getelementptr half, ptr addrspace(1) %out, i32 %tid - %a = load volatile half, ptr addrspace(1) %gep0 - %b = load volatile half, ptr addrspace(1) %gep1 - %c = load volatile half, ptr addrspace(1) %gep2 - - %a.fneg = fsub half -0.0, %a - %b.fabs = call half @llvm.fabs.f16(half %b) - %c.fabs = call half @llvm.fabs.f16(half %c) - %c.fabs.fneg = fsub half -0.0, %c.fabs - - %tmp0 = call half @llvm.minnum.f16(half %a.fneg, half %b.fabs) - %tmp1 = call half @llvm.maxnum.f16(half %a.fneg, half %b.fabs) - %tmp2 = call half @llvm.minnum.f16(half %tmp1, half %c.fabs.fneg) - %med3 = call half @llvm.maxnum.f16(half %tmp0, half %tmp2) - - store half %med3, ptr addrspace(1) %outgep - ret void -} - -define amdgpu_kernel void @v_test_global_nnans_med3_f16_pat0_negabs012(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #2 { -; SI-LABEL: v_test_global_nnans_med3_f16_pat0_negabs012: -; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 -; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: s_mov_b32 s10, 0 -; SI-NEXT: s_mov_b32 s11, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[2:3] -; SI-NEXT: buffer_load_ushort v2, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[4:5] -; SI-NEXT: buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[6:7] -; SI-NEXT: buffer_load_ushort v4, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e64 v2, -|v2| -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e64 v3, -|v3| -; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e64 v4, -|v4| -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_min_f32_e32 v5, v2, v3 -; SI-NEXT: v_max_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_min_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_max_f32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: s_mov_b64 s[2:3], s[10:11] -; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 -; SI-NEXT: s_endpgm -; -; VI-LABEL: v_test_global_nnans_med3_f16_pat0_negabs012: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; VI-NEXT: v_lshlrev_b32_e32 v6, 1, v0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v2, s4 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_mov_b32_e32 v5, s7 -; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 -; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; VI-NEXT: flat_load_ushort v7, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v2, v[2:3] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v3, v[4:5] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_max_f16_e64 v4, -|v7|, -|v7| -; VI-NEXT: v_max_f16_e64 v2, -|v2|, -|v2| -; VI-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| -; VI-NEXT: v_min_f16_e32 v5, v4, v2 -; VI-NEXT: v_max_f16_e32 v2, v4, v2 -; VI-NEXT: v_min_f16_e32 v2, v2, v3 -; VI-NEXT: v_max_f16_e32 v2, v5, v2 -; VI-NEXT: flat_store_short v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_test_global_nnans_med3_f16_pat0_negabs012: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_max_f16_e64 v1, -|v1|, -|v1| -; GFX9-NEXT: v_max_f16_e64 v2, -|v2|, -|v2| -; GFX9-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| -; GFX9-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX9-NEXT: global_store_short v0, v1, s[0:1] -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: v_test_global_nnans_med3_f16_pat0_negabs012: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_max_f16_e64 v1, -|v1|, -|v1| -; GFX10-NEXT: v_max_f16_e64 v2, -|v2|, -|v2| -; GFX10-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| -; GFX10-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX10-NEXT: global_store_short v0, v1, s[0:1] -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: v_test_global_nnans_med3_f16_pat0_negabs012: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v3, v0, s[6:7] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_max_f16_e64 v1, -|v1|, -|v1| -; GFX11-NEXT: v_max_f16_e64 v2, -|v2|, -|v2| -; GFX11-NEXT: v_max_f16_e64 v3, -|v3|, -|v3| -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid - %gep1 = getelementptr half, ptr addrspace(1) %bptr, i32 %tid - %gep2 = getelementptr half, ptr addrspace(1) %cptr, i32 %tid - %outgep = getelementptr half, ptr addrspace(1) %out, i32 %tid - %a = load volatile half, ptr addrspace(1) %gep0 - %b = load volatile half, ptr addrspace(1) %gep1 - %c = load volatile half, ptr addrspace(1) %gep2 - - %a.fabs = call half @llvm.fabs.f16(half %a) - %a.fabs.fneg = fsub half -0.0, %a.fabs - %b.fabs = call half @llvm.fabs.f16(half %b) - %b.fabs.fneg = fsub half -0.0, %b.fabs - %c.fabs = call half @llvm.fabs.f16(half %c) - %c.fabs.fneg = fsub half -0.0, %c.fabs - - %tmp0 = call half @llvm.minnum.f16(half %a.fabs.fneg, half %b.fabs.fneg) - %tmp1 = call half @llvm.maxnum.f16(half %a.fabs.fneg, half %b.fabs.fneg) - %tmp2 = call half @llvm.minnum.f16(half %tmp1, half %c.fabs.fneg) - %med3 = call half @llvm.maxnum.f16(half %tmp0, half %tmp2) - - store half %med3, ptr addrspace(1) %outgep - ret void -} - -define amdgpu_kernel void @v_nnan_inputs_med3_f16_pat0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #1 { -; SI-LABEL: v_nnan_inputs_med3_f16_pat0: -; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 -; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: s_mov_b32 s10, 0 -; SI-NEXT: s_mov_b32 s11, 0xf000 -; SI-NEXT: v_cvt_f32_f16_e32 v2, 1.0 -; SI-NEXT: v_cvt_f32_f16_e32 v3, 2.0 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[2:3] -; SI-NEXT: buffer_load_ushort v4, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v5, 4.0 -; SI-NEXT: s_mov_b64 s[8:9], s[4:5] -; SI-NEXT: buffer_load_ushort v6, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[6:7] -; SI-NEXT: buffer_load_ushort v7, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 -; SI-NEXT: v_add_f32_e32 v2, v4, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v6 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_add_f32_e32 v3, v4, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v7 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; SI-NEXT: v_add_f32_e32 v4, v4, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_min_f32_e32 v5, v2, v3 -; SI-NEXT: v_max_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_min_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_max_f32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: s_mov_b64 s[2:3], s[10:11] -; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 -; SI-NEXT: s_endpgm -; -; VI-LABEL: v_nnan_inputs_med3_f16_pat0: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; VI-NEXT: v_lshlrev_b32_e32 v6, 1, v0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v2, s4 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_mov_b32_e32 v5, s7 -; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 -; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; VI-NEXT: flat_load_ushort v7, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v2, v[2:3] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v3, v[4:5] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_add_f16_e32 v4, 1.0, v7 -; VI-NEXT: v_add_f16_e32 v2, 2.0, v2 -; VI-NEXT: v_add_f16_e32 v3, 4.0, v3 -; VI-NEXT: v_min_f16_e32 v5, v4, v2 -; VI-NEXT: v_max_f16_e32 v2, v4, v2 -; VI-NEXT: v_min_f16_e32 v2, v2, v3 -; VI-NEXT: v_max_f16_e32 v2, v5, v2 -; VI-NEXT: flat_store_short v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_nnan_inputs_med3_f16_pat0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_add_f16_e32 v1, 1.0, v1 -; GFX9-NEXT: v_add_f16_e32 v2, 2.0, v2 -; GFX9-NEXT: v_add_f16_e32 v3, 4.0, v3 -; GFX9-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX9-NEXT: global_store_short v0, v1, s[0:1] -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: v_nnan_inputs_med3_f16_pat0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add_f16_e32 v1, 1.0, v1 -; GFX10-NEXT: v_add_f16_e32 v2, 2.0, v2 -; GFX10-NEXT: v_add_f16_e32 v3, 4.0, v3 -; GFX10-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX10-NEXT: global_store_short v0, v1, s[0:1] -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: v_nnan_inputs_med3_f16_pat0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v3, v0, s[6:7] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_add_f16_e32 v1, 1.0, v1 -; GFX11-NEXT: v_add_f16_e32 v2, 2.0, v2 -; GFX11-NEXT: v_add_f16_e32 v3, 4.0, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_med3_f16 v1, v1, v2, v3 -; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid - %gep1 = getelementptr half, ptr addrspace(1) %bptr, i32 %tid - %gep2 = getelementptr half, ptr addrspace(1) %cptr, i32 %tid - %outgep = getelementptr half, ptr addrspace(1) %out, i32 %tid - %a = load volatile half, ptr addrspace(1) %gep0 - %b = load volatile half, ptr addrspace(1) %gep1 - %c = load volatile half, ptr addrspace(1) %gep2 - - %a.nnan = fadd nnan half %a, 1.0 - %b.nnan = fadd nnan half %b, 2.0 - %c.nnan = fadd nnan half %c, 4.0 - - %tmp0 = call half @llvm.minnum.f16(half %a.nnan, half %b.nnan) - %tmp1 = call half @llvm.maxnum.f16(half %a.nnan, half %b.nnan) - %tmp2 = call half @llvm.minnum.f16(half %tmp1, half %c.nnan) - %med3 = call half @llvm.maxnum.f16(half %tmp0, half %tmp2) - store half %med3, ptr addrspace(1) %outgep - ret void -} - - -; --------------------------------------------------------------------- -; Negative patterns -; --------------------------------------------------------------------- - -define amdgpu_kernel void @v_test_safe_med3_f16_pat0_multi_use0(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #1 { -; SI-LABEL: v_test_safe_med3_f16_pat0_multi_use0: -; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 -; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; SI-NEXT: v_mov_b32_e32 v1, 0 -; SI-NEXT: s_mov_b32 s10, 0 -; SI-NEXT: s_mov_b32 s11, 0xf000 -; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[2:3] -; SI-NEXT: buffer_load_ushort v2, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b64 s[8:9], s[4:5] -; SI-NEXT: buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: s_mov_b32 s2, -1 -; SI-NEXT: s_mov_b32 s3, s11 -; SI-NEXT: s_mov_b64 s[8:9], s[6:7] -; SI-NEXT: buffer_load_ushort v4, v[0:1], s[8:11], 0 addr64 glc -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_min_f32_e32 v5, v2, v3 -; SI-NEXT: v_max_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: buffer_store_short v4, off, s[0:3], 0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_min_f32_e32 v2, v2, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_max_f32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: s_mov_b64 s[2:3], s[10:11] -; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 -; SI-NEXT: s_endpgm -; -; VI-LABEL: v_test_safe_med3_f16_pat0_multi_use0: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; VI-NEXT: v_lshlrev_b32_e32 v6, 1, v0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s2 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_mov_b32_e32 v2, s4 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 -; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_mov_b32_e32 v5, s7 -; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 -; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; VI-NEXT: flat_load_ushort v7, v[0:1] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v2, v[2:3] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_load_ushort v3, v[4:5] glc -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 -; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_max_f16_e32 v4, v7, v7 -; VI-NEXT: v_max_f16_e32 v2, v2, v2 -; VI-NEXT: v_max_f16_e32 v3, v3, v3 -; VI-NEXT: v_min_f16_e32 v5, v4, v2 -; VI-NEXT: v_max_f16_e32 v2, v4, v2 -; VI-NEXT: v_min_f16_e32 v2, v2, v3 -; VI-NEXT: v_max_f16_e32 v2, v5, v2 -; VI-NEXT: flat_store_short v[0:1], v5 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: flat_store_short v[0:1], v2 -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_test_safe_med3_f16_pat0_multi_use0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v2, v0, s[4:5] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: global_load_ushort v3, v0, s[6:7] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX9-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX9-NEXT: v_max_f16_e32 v3, v3, v3 -; GFX9-NEXT: v_min_f16_e32 v4, v1, v2 -; GFX9-NEXT: v_max_f16_e32 v1, v1, v2 -; GFX9-NEXT: global_store_short v[0:1], v4, off -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_min_f16_e32 v1, v1, v3 -; GFX9-NEXT: v_max_f16_e32 v1, v4, v1 -; GFX9-NEXT: global_store_short v0, v1, s[0:1] -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: v_test_safe_med3_f16_pat0_multi_use0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v2, v0, s[4:5] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_load_ushort v3, v0, s[6:7] glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX10-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX10-NEXT: v_max_f16_e32 v3, v3, v3 -; GFX10-NEXT: v_max_f16_e32 v4, v1, v2 -; GFX10-NEXT: v_min_f16_e32 v1, v1, v2 -; GFX10-NEXT: v_min_f16_e32 v2, v4, v3 -; GFX10-NEXT: v_max_f16_e32 v2, v1, v2 -; GFX10-NEXT: global_store_short v[0:1], v1, off -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: global_store_short v0, v2, s[0:1] -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: v_test_safe_med3_f16_pat0_multi_use0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_u16 v3, v0, s[6:7] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX11-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_min_f16_e32 v4, v1, v2 -; GFX11-NEXT: v_max_f16_e32 v1, v1, v2 -; GFX11-NEXT: v_max_f16_e32 v2, v3, v3 -; GFX11-NEXT: v_minmax_f16 v1, v1, v2, v4 -; GFX11-NEXT: global_store_b16 v[0:1], v4, off dlc -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm - %tid = call i32 @llvm.amdgcn.workitem.id.x() - %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid - %gep1 = getelementptr half, ptr addrspace(1) %bptr, i32 %tid - %gep2 = getelementptr half, ptr addrspace(1) %cptr, i32 %tid - %outgep = getelementptr half, ptr addrspace(1) %out, i32 %tid - %a = load volatile half, ptr addrspace(1) %gep0 - %b = load volatile half, ptr addrspace(1) %gep1 - %c = load volatile half, ptr addrspace(1) %gep2 - %tmp0 = call half @llvm.minnum.f16(half %a, half %b) - store volatile half %tmp0, ptr addrspace(1) undef - %tmp1 = call half @llvm.maxnum.f16(half %a, half %b) - %tmp2 = call half @llvm.minnum.f16(half %tmp1, half %c) - %med3 = call half @llvm.maxnum.f16(half %tmp0, half %tmp2) - store half %med3, ptr addrspace(1) %outgep - ret void -} - -declare i32 @llvm.amdgcn.workitem.id.x() #0 -declare half @llvm.fabs.f16(half) #0 -declare half @llvm.minnum.f16(half, half) #0 -declare half @llvm.maxnum.f16(half, half) #0 - -attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="false" } -attributes #2 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="true" }