From: Hal Feng <hal.feng@starfivetech.com>
Date: Sun, 19 Feb 2023 14:47:33 +0000 (+0800)
Subject: dt-bindings: riscv: Add SiFive S7 compatible
X-Git-Tag: accepted/tizen/unified/riscv/20230725.071352~222
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8aeade2fe6fd58d75ff54decbf061cd9cd01e4f9;p=platform%2Fkernel%2Flinux-starfive.git

dt-bindings: riscv: Add SiFive S7 compatible

Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d4148418350c..f01ee5882e40 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -34,9 +34,11 @@ properties:
               - sifive,e7
               - sifive,e71
               - sifive,u74-mc
+              - sifive,rocket0
+              - sifive,s7
+              - sifive,u5
               - sifive,u54
               - sifive,u74
-              - sifive,u5
               - sifive,u7
               - canaan,k210
           - const: riscv