From: Chia-I Wu <olv@lunarg.com>
Date: Mon, 2 Mar 2015 18:19:33 +0000 (-0700)
Subject: intel: determine 3DSTATE_MULTISAMPLE from intel_fb
X-Git-Tag: sdk-0.1.0~357
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8ada424c4d577871b2bd4da8f08f2b595e796df1;p=platform%2Fupstream%2FVulkan-LoaderAndValidationLayers.git

intel: determine 3DSTATE_MULTISAMPLE from intel_fb
---

diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index af96ded..c3f7c4b 100644
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -720,6 +720,43 @@ static void gen7_3DSTATE_PS(struct intel_cmd *cmd)
         gen6_add_scratch_space(cmd, pos + 3, pipeline, fs);
 }
 
+static void gen6_3DSTATE_MULTISAMPLE(struct intel_cmd *cmd,
+                                     uint32_t sample_count)
+{
+    const uint8_t cmd_len = (cmd_gen(cmd) >= INTEL_GEN(7)) ? 4 : 3;
+    uint32_t dw1, dw2, dw3, *dw;
+
+    CMD_ASSERT(cmd, 6, 7.5);
+
+    switch (sample_count) {
+    case 4:
+        dw1 = GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4;
+        dw2 = cmd->dev->sample_pattern_4x;
+        dw3 = 0;
+        break;
+    case 8:
+        assert(cmd_gen(cmd) >= INTEL_GEN(7));
+        dw1 = GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8;
+        dw2 = cmd->dev->sample_pattern_8x[0];
+        dw3 = cmd->dev->sample_pattern_8x[1];
+        break;
+    default:
+        assert(sample_count <= 1);
+        dw1 = GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
+        dw2 = 0;
+        dw3 = 0;
+        break;
+    }
+
+    cmd_batch_pointer(cmd, cmd_len, &dw);
+
+    dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) | (cmd_len - 2);
+    dw[1] = dw1;
+    dw[2] = dw2;
+    if (cmd_gen(cmd) >= INTEL_GEN(7))
+        dw[3] = dw3;
+}
+
 static void gen6_3DSTATE_DEPTH_BUFFER(struct intel_cmd *cmd,
                                       const struct intel_ds_view *view,
                                       bool optimal_ds)
@@ -1835,6 +1872,17 @@ static void emit_shader_resources(struct intel_cmd *cmd)
     }
 }
 
+static void emit_msaa(struct intel_cmd *cmd)
+{
+    const struct intel_fb *fb = cmd->bind.render_pass->fb;
+
+    if (fb->sample_count != cmd->bind.pipeline.graphics->sample_count)
+        cmd->result = XGL_ERROR_UNKNOWN;
+
+    cmd_wa_gen6_pre_multisample_depth_flush(cmd);
+    gen6_3DSTATE_MULTISAMPLE(cmd, fb->sample_count);
+}
+
 static void emit_rt(struct intel_cmd *cmd)
 {
     cmd_wa_gen6_pre_depth_stall_write(cmd);
@@ -1953,6 +2001,7 @@ static void emit_graphics_pipeline(struct intel_cmd *cmd)
 
 static void emit_bounded_states(struct intel_cmd *cmd)
 {
+    emit_msaa(cmd);
 
     emit_graphics_pipeline(cmd);
 
@@ -1989,7 +2038,6 @@ static void emit_bounded_states(struct intel_cmd *cmd)
     emit_shader_resources(cmd);
 
     cmd_wa_gen6_pre_depth_stall_write(cmd);
-    cmd_wa_gen6_pre_multisample_depth_flush(cmd);
 
     gen6_3DSTATE_VERTEX_BUFFERS(cmd);
     gen6_3DSTATE_VS(cmd);
diff --git a/icd/intel/pipeline.c b/icd/intel/pipeline.c
index 7a6e60c..f8c8f6e 100644
--- a/icd/intel/pipeline.c
+++ b/icd/intel/pipeline.c
@@ -1109,42 +1109,13 @@ static void pipeline_build_msaa(struct intel_pipeline *pipeline,
 
     INTEL_GPU_ASSERT(pipeline->dev->gpu, 6, 7.5);
 
-
-    pipeline->sample_count = (info->ms.samples <= 1)?1:info->ms.samples;
-
-    /* 3DSTATE_MULTISAMPLE */
-    cmd = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE);
-    cmd_len = (intel_gpu_gen(pipeline->dev->gpu) >= INTEL_GEN(7)) ? 4 : 3;
-    dw = pipeline_cmd_ptr(pipeline, cmd_len + 2);
-    dw[0] = cmd | (cmd_len - 2);
-    if (pipeline->sample_count <= 1)
-        dw[1] = GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
-    else if (pipeline->sample_count <= 4 || intel_gpu_gen(pipeline->dev->gpu) == INTEL_GEN(6))
-        dw[1] = GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4;
-    else
-        dw[1] = GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8;
-
-    switch (pipeline->sample_count) {
-    case 2:
-        dw[2] = pipeline->dev->sample_pattern_2x;
-        break;
-    case 4:
-        dw[2] = pipeline->dev->sample_pattern_4x;
-        break;
-    case 8:
-        dw[2] = pipeline->dev->sample_pattern_8x[0];
-        dw[3] = pipeline->dev->sample_pattern_8x[1];
-        break;
-    default:
-        break;
-    }
-
-    dw += cmd_len;
+    pipeline->sample_count = (info->ms.samples <= 1) ? 1 : info->ms.samples;
 
     /* 3DSTATE_SAMPLE_MASK */
     cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK);
     cmd_len = 2;
 
+    dw = pipeline_cmd_ptr(pipeline, cmd_len);
     dw[0] = cmd | (cmd_len - 2);
     dw[1] = info->ms.sampleMask & ((1 << pipeline->sample_count) - 1);
     pipeline->cmd_sample_mask = dw[1];
diff --git a/icd/intel/pipeline.h b/icd/intel/pipeline.h
index 64bf757..c43d54e 100644
--- a/icd/intel/pipeline.h
+++ b/icd/intel/pipeline.h
@@ -150,7 +150,6 @@ struct intel_pipeline_shader {
  *
  *  - 3DSTATE_URB (3)
  *  - 3DSTATE_VERTEX_ELEMENTS (1+2*INTEL_MAX_VERTEX_ELEMENT_COUNT)
- *  - 3DSTATE_MULTISAMPLE (3)
  *  - 3DSTATE_SAMPLE_MASK (2)
  *
  * On GEN7, there are
@@ -162,7 +161,6 @@ struct intel_pipeline_shader {
  *  - 3DSTATE_HS (7)
  *  - 3DSTATE_TE (4)
  *  - 3DSTATE_DS (6)
- *  - 3DSTATE_MULTISAMPLE (4)
  *  - 3DSTATE_SAMPLE_MASK (2)
  */
 #define INTEL_PSO_CMD_ENTRIES   128