From: Sean Anderson <sean.anderson@seco.com>
Date: Mon, 7 Jun 2021 19:05:46 +0000 (-0400)
Subject: dt-bindings: clk: vc5: Fix example
X-Git-Tag: v5.15~817^2~12
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=89f8a707d00890d302f6d4320d4ecdba12c26bdf;p=platform%2Fkernel%2Flinux-starfive.git

dt-bindings: clk: vc5: Fix example

The example properties do not match the binding. Fix them, and prohibit
undocumented properties in clock nodes to prevent this from happening in
the future.

Fixes: 45c940184b50 ("dt-bindings: clk: versaclock5: convert to yaml")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20210607190546.2616259-1-sean.anderson@seco.com
Signed-off-by: Rob Herring <robh@kernel.org>
---

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
index c268deb..241e1f2 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
@@ -86,6 +86,7 @@ patternProperties:
         description: The Slew rate control for CMOS single-ended.
         $ref: /schemas/types.yaml#/definitions/uint32
         enum: [ 80, 85, 90, 100 ]
+    additionalProperties: false
 
 required:
   - compatible
@@ -141,13 +142,13 @@ examples:
             clock-names = "xin";
 
             OUT1 {
-                idt,drive-mode = <VC5_CMOSD>;
-                idt,voltage-microvolts = <1800000>;
+                idt,mode = <VC5_CMOSD>;
+                idt,voltage-microvolt = <1800000>;
                 idt,slew-percent = <80>;
             };
 
             OUT4 {
-                idt,drive-mode = <VC5_LVDS>;
+                idt,mode = <VC5_LVDS>;
             };
         };
     };