From: Andrew Bresticker <abrestic@chromium.org>
Date: Fri, 27 Dec 2013 00:44:26 +0000 (-0800)
Subject: clk: tegra: cclk_lp has a pllx/2 divider
X-Git-Tag: v3.14-rc6~35^2~4^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=88b4bd7071ac06e321b4bf4bdb8c69db40182c5a;p=profile%2Fivi%2Fkernel-x86-ivi.git

clk: tegra: cclk_lp has a pllx/2 divider

When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2.  Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---

diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
index 05dce4a..feb3201 100644
--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -120,7 +120,7 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
 					ARRAY_SIZE(cclk_lp_parents),
 					CLK_SET_RATE_PARENT,
 					clk_base + CCLKLP_BURST_POLICY,
-					0, 4, 8, 9, NULL);
+					TEGRA_DIVIDER_2, 4, 8, 9, NULL);
 		*dt_clk = clk;
 	}