From: Hyunjun Ko <zzoon@igalia.com>
Date: Wed, 15 Sep 2021 06:56:09 +0000 (+0000)
Subject: freedreno/a5xx,a6xx: rename MSAA_ENABLE to LINE_MODE in GRAS_SU_CNTL
X-Git-Tag: upstream/22.3.5~16675
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=88afceacf04ecbd5a31656749a56326fe2320428;p=platform%2Fupstream%2Fmesa.git

freedreno/a5xx,a6xx: rename MSAA_ENABLE to LINE_MODE in GRAS_SU_CNTL

This bit seems like the control for line mode of rastrization.

That can be simply figured out by comparing
dEQP-VK.rasterization.primitives.no_stipple.bresenham_lines,
dEQP-VK.rasterization.primitives.no_stipple.rectangular_lines and
dEQP-VK.rasterization.primitives.no_stipple.lines.

For opengl, the value of bresenham lines mode, which is 0, is set
by default and the value of rectangular mode, which is 0x1, is set
when multi-sampled.

For vulkan, the bresenham lines are enabled when lineRasterizationMode is
VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT, which sets the bit to 0, while
the value is 1 when it's VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT,
that seems to be default.

If both multi-sampled and bresenham-lines are used when primitive type is
line, the bit is to be set as 0 and makes msaa disabled.

Note that this is only tested on a6xx, but I guess it's likely the same
for a5xx.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6020>
---

diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index 21482da..aa369c8 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -5382,7 +5382,7 @@ clusters:
 	00000000	GRAS_CL_Z_CLAMP[0xe].MAX: 0.000000
 	00000000	GRAS_CL_Z_CLAMP[0xf].MIN: 0.000000
 	00000000	GRAS_CL_Z_CLAMP[0xf].MAX: 0.000000
-	00000010	GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 }
+	00000010	GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
 	00000000	GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 	00000000	GRAS_SU_POINT_SIZE: 0.000000
 	00000000	GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
@@ -5627,7 +5627,7 @@ clusters:
 	00000000	GRAS_CL_Z_CLAMP[0xe].MAX: 0.000000
 	00000000	GRAS_CL_Z_CLAMP[0xf].MIN: 0.000000
 	00000000	GRAS_CL_Z_CLAMP[0xf].MAX: 0.000000
-	00000010	GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 }
+	00000010	GRAS_SU_CNTL: { LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
 	00000000	GRAS_SU_POINT_MINMAX: { MIN = 0.000000 | MAX = 0.000000 }
 	00000000	GRAS_SU_POINT_SIZE: 0.000000
 	00000000	GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
index 647c45e..528661e 100644
--- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
@@ -1214,7 +1214,7 @@ t4					write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
 			enable_mask: 0x7
 0000000001054730:				0000: 40809001 00000814
 t4					write GRAS_SU_CNTL (8090)
-						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET }
+						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET | LINE_MODE = BRESENHAM }
 0000000001054730:					0000: 40809001 00000814
 			group_id: 22
 			count: 4
@@ -1323,7 +1323,7 @@ t7			opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
 !+	3f800000			GRAS_CL_VPORT[0].ZSCALE: 1.000000
  +	00000000			GRAS_CL_Z_CLAMP[0].MIN: 0.000000
 !+	3f800000			GRAS_CL_Z_CLAMP[0].MAX: 1.000000
-!+	00000814			GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET }
+!+	00000814			GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET | LINE_MODE = BRESENHAM }
 !+	ffc00001			GRAS_SU_POINT_MINMAX: { MIN = 0.062500 | MAX = 4092.000000 }
 !+	00000010			GRAS_SU_POINT_SIZE: 1.000000
  +	00000000			GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
index 1ac9b28..a5d53c3 100644
--- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log
+++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
@@ -819,7 +819,7 @@ t4					write GRAS_CL_CNTL (8000)
 						GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
 0000000001123000:					0000: 40800002 00000080 00000000
 t4					write GRAS_SU_CNTL (8090)
-						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 }
+						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
 000000000112300c:					0000: 40809001 00000014
 t4					write GRAS_SU_POINT_MINMAX (8091)
 						GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
@@ -930,7 +930,7 @@ t7			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 !+	44340000			GRAS_CL_VPORT[0].YSCALE: 720.000000
 !+	3f000000			GRAS_CL_VPORT[0].ZOFFSET: 0.500000
 !+	3f000000			GRAS_CL_VPORT[0].ZSCALE: 0.500000
-!+	00000014			GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 }
+!+	00000014			GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
 !+	00100010			GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
 !+	00000010			GRAS_SU_POINT_SIZE: 1.000000
  +	00000000			GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
@@ -5060,7 +5060,7 @@ t4					write GRAS_CL_CNTL (8000)
 						GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
 0000000001123000:					0000: 40800002 00000080 00000000
 t4					write GRAS_SU_CNTL (8090)
-						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 }
+						GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
 000000000112300c:					0000: 40809001 00000014
 t4					write GRAS_SU_POINT_MINMAX (8091)
 						GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
@@ -5181,7 +5181,7 @@ t7			opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
  +	44340000			GRAS_CL_VPORT[0].YSCALE: 720.000000
  +	3f000000			GRAS_CL_VPORT[0].ZOFFSET: 0.500000
  +	3f000000			GRAS_CL_VPORT[0].ZSCALE: 0.500000
- +	00000014			GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 }
+ +	00000014			GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | LINE_MODE = BRESENHAM }
  +	00100010			GRAS_SU_POINT_MINMAX: { MIN = 1.000000 | MAX = 1.000000 }
  +	00000010			GRAS_SU_POINT_SIZE: 1.000000
  +	00000000			GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
diff --git a/src/freedreno/registers/adreno/a5xx.xml b/src/freedreno/registers/adreno/a5xx.xml
index 87200b1..b85f195 100644
--- a/src/freedreno/registers/adreno/a5xx.xml
+++ b/src/freedreno/registers/adreno/a5xx.xml
@@ -1846,7 +1846,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 		<bitfield name="FRONT_CW" pos="2" type="boolean"/>
 		<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
 		<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
-		<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
+		<bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
 		<!-- probably LINEHALFWIDTH is the same as a4xx.. -->
 	</reg32>
 	<reg32 offset="0xe091" name="GRAS_SU_POINT_MINMAX">
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 8aea49a..4724675 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1597,7 +1597,7 @@ to upconvert to 32b float internally?
 		<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
 		<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
 		<bitfield name="UNK12" pos="12"/>
-		<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
+		<bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
 		<bitfield name="UNK15" low="15" high="16"/>
 		<!--
 		This is set by the blob when multiview is enabled, but doesn't seem
diff --git a/src/freedreno/registers/adreno/adreno_common.xml b/src/freedreno/registers/adreno/adreno_common.xml
index d70fbaf..d9fc4ab 100644
--- a/src/freedreno/registers/adreno/adreno_common.xml
+++ b/src/freedreno/registers/adreno/adreno_common.xml
@@ -366,5 +366,14 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value name="ADDR_64B" value="1"/>
 </enum>
 
+<doc>
+    Line mode for a5xx+
+	Note that Bresenham lines are only supported with MSAA disabled.
+</doc>
+<enum name="a5xx_line_mode">
+	<value value="0x0"  name="BRESENHAM"/>
+	<value value="0x1"  name="RECTANGULAR"/>
+</enum>
+
 </database>
 
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index d490f5c..bbc4dd8 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1990,7 +1990,7 @@ tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
       gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
 
    if (samples > VK_SAMPLE_COUNT_1_BIT)
-      gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
+      gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINE_MODE(RECTANGULAR);
 
    if (multiview) {
       gras_su_cntl |=
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
index d2a8a2f..84b024c 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
@@ -184,7 +184,8 @@ fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
    OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
    OUT_RING(ring,
             A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0) |
-               COND(zsbuf->b.b.nr_samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
+               A5XX_GRAS_SU_CNTL_LINE_MODE(zsbuf->b.b.nr_samples  > 1 ?
+                                           RECTANGULAR : BRESENHAM));
 
    OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
    OUT_RING(ring, 0x00000000);
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 08e1173..9e27308 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -667,7 +667,8 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
       OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
       OUT_RING(ring, rasterizer->gras_su_cntl |
-                        COND(pfb->samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
+                        A5XX_GRAS_SU_CNTL_LINE_MODE(pfb->samples > 1 ?
+                                                    RECTANGULAR : BRESENHAM));
 
       OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
       OUT_RING(ring, rasterizer->gras_su_point_minmax);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
index 7ef8a30..a1142f7 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
@@ -61,7 +61,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
    OUT_REG(ring,
            A6XX_GRAS_SU_CNTL(.linehalfwidth = cso->line_width / 2.0,
                              .poly_offset = cso->offset_tri,
-                             .msaa_enable = cso->multisample,
+                             .line_mode = cso->multisample ? RECTANGULAR : BRESENHAM,
                              .cull_front = cso->cull_face & PIPE_FACE_FRONT,
                              .cull_back = cso->cull_face & PIPE_FACE_BACK,
                              .front_cw = !cso->front_ccw, ));