From: Simon Pilgrim Date: Thu, 10 Nov 2016 14:19:45 +0000 (+0000) Subject: [DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL X-Git-Tag: llvmorg-4.0.0-rc1~5041 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=87f38fa85cbdc5ef979d6fc463733716863c481e;p=platform%2Fupstream%2Fllvm.git [DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL Fails to match constant shift value due to presence of AND mask. llvm-svn: 286452 --- diff --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll index 64ed1ce..a35a309 100644 --- a/llvm/test/CodeGen/X86/combine-shl.ll +++ b/llvm/test/CodeGen/X86/combine-shl.ll @@ -44,6 +44,21 @@ define <4 x i32> @combine_vec_shl_outofrange1(<4 x i32> %x) { ret <4 x i32> %1 } +define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) { +; SSE-LABEL: combine_vec_shl_outofrange2: +; SSE: # BB#0: +; SSE-NEXT: xorps %xmm0, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: combine_vec_shl_outofrange2: +; AVX: # BB#0: +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = and <4 x i32> %a0, + %2 = shl <4 x i32> %1, + ret <4 x i32> %2 +} + ; fold (shl x, 0) -> x define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) { ; SSE-LABEL: combine_vec_shl_by_zero: