From: Timur Kristóf Date: Mon, 3 Apr 2023 15:47:10 +0000 (+0200) Subject: radv: Create continue preamble on GFX6 even when no shader rings are used. X-Git-Tag: upstream/23.3.3~10173 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=87d22933aedd461ec07464236493fd88e52503d0;p=platform%2Fupstream%2Fmesa.git radv: Create continue preamble on GFX6 even when no shader rings are used. Skipping the continue preamble can allow other processes to mess up some registers set by the current process. Originally, we could omit generating the continue preamble when no shader rings were used, because the register initialization happened at the beginning of every main cmdbuf. However, this isn't the case anymore. Cc: mesa-stable Signed-off-by: Timur Kristóf Reviewed-by: Bas Nieuwenhuizen Part-of: --- diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index e49c536..f6960d3 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -1069,12 +1069,6 @@ radv_update_preamble_cs(struct radv_queue_state *queue, struct radv_device *devi if (!(device->instance->debug_flags & RADV_DEBUG_NO_IBS) && device->physical_device->rad_info.gfx_level >= GFX7) continue; - /* Continue preamble is unnecessary when no shader rings are used. */ - if (!needs->scratch_size_per_wave && !needs->compute_scratch_size_per_wave && - !needs->esgs_ring_size && !needs->gsvs_ring_size && !needs->tess_rings && - !needs->task_rings && !needs->mesh_scratch_ring && !needs->attr_ring_size && - !needs->gds && !needs->gds_oa && !needs->sample_positions) - continue; } enum rgp_flush_bits sqtt_flush_bits = 0;