From: Wolfgang Denk Date: Thu, 27 Oct 2011 22:15:19 +0000 (+0200) Subject: Merge branch 'master' of git://git.denx.de/u-boot-arm X-Git-Tag: v2011.12-rc1~343 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=87a5d601031652293ec4b729fdb7ee01bbd940a8;hp=-c;p=platform%2Fkernel%2Fu-boot.git Merge branch 'master' of git://git.denx.de/u-boot-arm * 'master' of git://git.denx.de/u-boot-arm: ARM: Add Calxeda Highbank platform dkb: make mmc command as default enabled Marvell: dkb: add mmc support ARM: pantheon: add mmc definition davinci: remove config.mk file from the sources ARM:AM33XX: Add support for TI AM335X EVM ARM:AM33XX: Added timer support ARM:AM33XX: Add emif/ddr support ARM:AM33XX: Add clock definitions ARM:AM33XX: Added support for AM33xx omap3/emif4: fix registers definition davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM davinci: emac: add support for more than 1 PHYs davinci: emac: add new features to autonegotiate for EMAC da850evm: Move LPSC configuration to board_early_init_f() omap4_panda: Build in cmd_gpio support on panda omap: Don't use gpio_free to change direction to input mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset OMAP3: overo : Add environment variable optargs to bootargs OMAP3: overo: Move ethernet CS4 configuration to execute based on board id OMAP3: overo : Use ttyO2 instead of ttyS2. da830: add support for NAND boot mode dm36x: revert cache disable patch dm644X: revert cache disable patch devkit8000: Add malloc space omap: spl: fix build break due to changes in FAT OMAP3 SPL: Provide weak omap_rev_string omap: beagle: Use ubifs instead of jffs2 for nand boot omap: overo: Disable pull-ups on camera PCLK, HS and VS signals omap: overo: Configure mux for gpio10 SPL: Add DMA library omap3: Add interface for omap3 DMA omap3: Add DMA register accessors omap3: Add Base register for DMA arm, davinci: add missing LSPC define for MMC/SD1 U-Boot/SPL: omap4: Make ddr pre-calculated timings as default. DaVinci: correct MDSTAT.STATE mask omap4: splitting padconfs into common, 4430 and 4460 omap4: adding revision detection for 4460 ES1.1 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL gplug: fixed build error as a result of code cleanup patch kirkwood_spi: add dummy spi_init() gpio: mvmfp: reduce include platform file ARM: orion5x: reduce dependence of including platform file serial: reduce include platform file for marvell chip ARM: kirkwood: reduce dependence of including platform file ARM: armada100: reduce dependence of including platform file ARM: pantheon: reduce dependence of including platform file Armada100: Add env storage support for Marvell gplugD Armada100: Add SPI flash support for Marvell gplugD Armada100: Add SPI support for Marvell gplugD SPI: Add SPI driver support for Marvell Armada100 dreamplug: initial board support. imx: fix coding style misc: pmic: drop old Freescale's pmic driver MX31: mx31pdk: use new pmic driver MX31: mx31ads: use new pmic driver MX31: mx31_litekit: use new pmic driver MX5: mx53evk: use new pmic driver MX5: mx51evk: use new pmic driver MX35: mx35pdk: use new pmic driver misc: pmic: addI2C support to pmic_fsl driver misc: pmic: use I2C_SET_BUS in pmic I2C MX5: efikamx/efikasb: use new pmic driver MX3: qong: use new pmic driver RTC: Switch mc13783 to generic pmic code MX5: vision2: use new pmic driver misc: pmic: Freescale PMIC switches to generic PMIC driver misc:pmic:samsung Enable PMIC driver at GONI target misc:pmic:max8998 MAX8998 support at a new PMIC driver. misc:pmic:core New generic PMIC driver mx31pdk: Remove unneeded config mx31: provide readable WEIM CS accessor MX51: vision2: Set global macros I2C: Add i2c_get/set_speed() to mxc_i2c.c ARM: Update mach-types devkit8000: Add config to enable SPL MMC boot devkit8000: protect board_mmc_init arm, post: add missing post_time_ms for arm cosmetic, post: Codingstyle cleanup arm, logbuffer: make it compileclean tegra2: Enable MMC for Seaboard tegra2: Add more pinmux functions tegra2: Rename PIN_ to PINGRP_ tegra2: Add more clock functions tegra2: Clean up board code a little tegra2: Rename CLOCK_PLL_ID to CLOCK_ID --- 87a5d601031652293ec4b729fdb7ee01bbd940a8 diff --combined arch/arm/lib/board.c index 368fc5d,9b16d75..a482706 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@@ -82,7 -82,6 +82,6 @@@ extern void rtl8019_get_enetaddr (ucha #include #endif - /************************************************************************ * Coloured LED functionality ************************************************************************ @@@ -590,7 -589,7 +589,7 @@@ void board_init_r(gd_t *id, ulong dest_ } #endif -#ifdef BOARD_LATE_INIT +#ifdef CONFIG_BOARD_LATE_INIT board_late_init(); #endif diff --combined board/freescale/mx35pdk/mx35pdk.c index 2ce6e8e,84a50b6..a5b51a0 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@@ -30,6 -30,7 +30,7 @@@ #include #include #include + #include #include #include #include @@@ -38,8 -39,8 +39,8 @@@ #include #include -#ifndef BOARD_LATE_INIT -#error "BOARD_LATE_INIT must be set for this board" +#ifndef CONFIG_BOARD_LATE_INIT +#error "CONFIG_BOARD_LATE_INIT must be set for this board" #endif #ifndef CONFIG_BOARD_EARLY_INIT_F @@@ -202,9 -203,10 +203,10 @@@ int board_init(void static inline int pmic_detect(void) { - int id; + unsigned int id; + struct pmic *p = get_pmic(); - id = pmic_reg_read(REG_IDENTIFICATION); + pmic_reg_read(p, REG_IDENTIFICATION, &id); id = (id >> 6) & 0x7; if (id == 0x7) @@@ -225,15 -227,19 +227,19 @@@ int board_late_init(void { u8 val; u32 pmic_val; + struct pmic *p; + pmic_init(); if (pmic_detect()) { + p = get_pmic(); mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | MUX_CONFIG_ALT1); - pmic_val = pmic_reg_read(REG_SETTING_0); - pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V); - pmic_val = pmic_reg_read(REG_MODE_0); - pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN); + pmic_reg_read(p, REG_SETTING_0, &pmic_val); + pmic_reg_write(p, REG_SETTING_0, + pmic_val | VO_1_30V | VO_1_50V); + pmic_reg_read(p, REG_MODE_0, &pmic_val); + pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN); mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); diff --combined board/freescale/mx51evk/mx51evk.c index f998610,73ca513..2a0dad0 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@@ -32,6 -32,7 +32,7 @@@ #include #include #include + #include #include #include @@@ -182,34 -183,38 +183,38 @@@ static void power_init(void { unsigned int val; struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + struct pmic *p; + + pmic_init(); + p = get_pmic(); /* Write needed to Power Gate 2 register */ - val = pmic_reg_read(REG_POWER_MISC); + pmic_reg_read(p, REG_POWER_MISC, &val); val &= ~PWGT2SPIEN; - pmic_reg_write(REG_POWER_MISC, val); + pmic_reg_write(p, REG_POWER_MISC, val); /* Externally powered */ - val = pmic_reg_read(REG_CHARGE); + pmic_reg_read(p, REG_CHARGE, &val); val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; - pmic_reg_write(REG_CHARGE, val); + pmic_reg_write(p, REG_CHARGE, val); /* power up the system first */ - pmic_reg_write(REG_POWER_MISC, PWUP); + pmic_reg_write(p, REG_POWER_MISC, PWUP); /* Set core voltage to 1.1V */ - val = pmic_reg_read(REG_SW_0); + pmic_reg_read(p, REG_SW_0, &val); val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; - pmic_reg_write(REG_SW_0, val); + pmic_reg_write(p, REG_SW_0, val); /* Setup VCC (SW2) to 1.25 */ - val = pmic_reg_read(REG_SW_1); + pmic_reg_read(p, REG_SW_1, &val); val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(REG_SW_1, val); + pmic_reg_write(p, REG_SW_1, val); /* Setup 1V2_DIG1 (SW3) to 1.25 */ - val = pmic_reg_read(REG_SW_2); + pmic_reg_read(p, REG_SW_2, &val); val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(REG_SW_2, val); + pmic_reg_write(p, REG_SW_2, val); udelay(50); /* Raise the core frequency to 800MHz */ @@@ -217,36 -222,36 +222,36 @@@ /* Set switchers in Auto in NORMAL mode & STANDBY mode */ /* Setup the switcher mode for SW1 & SW2*/ - val = pmic_reg_read(REG_SW_4); + pmic_reg_read(p, REG_SW_4, &val); val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | (SWMODE_MASK << SWMODE2_SHIFT))); val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - pmic_reg_write(REG_SW_4, val); + pmic_reg_write(p, REG_SW_4, val); /* Setup the switcher mode for SW3 & SW4 */ - val = pmic_reg_read(REG_SW_5); + pmic_reg_read(p, REG_SW_5, &val); val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | (SWMODE_MASK << SWMODE4_SHIFT))); val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); - pmic_reg_write(REG_SW_5, val); + pmic_reg_write(p, REG_SW_5, val); /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ - val = pmic_reg_read(REG_SETTING_0); + pmic_reg_read(p, REG_SETTING_0, &val); val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; - pmic_reg_write(REG_SETTING_0, val); + pmic_reg_write(p, REG_SETTING_0, val); /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ - val = pmic_reg_read(REG_SETTING_1); + pmic_reg_read(p, REG_SETTING_1, &val); val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; - pmic_reg_write(REG_SETTING_1, val); + pmic_reg_write(p, REG_SETTING_1, val); /* Configure VGEN3 and VCAM regulators to use external PNP */ val = VGEN3CONFIG | VCAMCONFIG; - pmic_reg_write(REG_MODE_1, val); + pmic_reg_write(p, REG_MODE_1, val); udelay(200); gpio_direction_output(46, 0); @@@ -257,7 -262,7 +262,7 @@@ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | VVIDEOEN | VAUDIOEN | VSDEN; - pmic_reg_write(REG_MODE_1, val); + pmic_reg_write(p, REG_MODE_1, val); udelay(500); @@@ -409,7 -414,7 +414,7 @@@ int board_init(void return 0; } -#ifdef BOARD_LATE_INIT +#ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { #ifdef CONFIG_MXC_SPI diff --combined board/imx31_phycore/imx31_phycore.c index 47f1a8d,a697e47..c165590 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@@ -27,6 -27,7 +27,7 @@@ #include #include #include + #include DECLARE_GLOBAL_DATA_PTR; @@@ -49,17 -50,39 +50,39 @@@ int board_init(void int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0x10000d03; - __REG(CSCR_A(0)) = 0x00720900; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + /* CS1: Network Controller */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; - __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ - __REG(CSCR_L(1)) = 0x444a4541; - __REG(CSCR_A(1)) = 0x44443302; + /* CS4: SRAM */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ - __REG(CSCR_L(4)) = 0x22252521; - __REG(CSCR_A(4)) = 0x22220a00; + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(1, &cs1); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); @@@ -74,7 -97,7 +97,7 @@@ return 0; } -#ifdef BOARD_LATE_INIT +#ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { #ifdef CONFIG_S6E63D6 diff --combined common/cmd_ide.c index 74e6504,d909c54..1fc0377 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@@ -46,12 -46,6 +46,6 @@@ #include #endif - #ifdef CONFIG_ORION5X - #include - #elif defined CONFIG_KIRKWOOD - #include - #endif - #include #include @@@ -1224,7 -1218,7 +1218,7 @@@ ulong ide_read (int device, lbaint_t bl lba48 = 1; } #endif - debug ("ide_read dev %d start %LX, blocks %lX buffer at %lX\n", + debug("ide_read dev %d start %lX, blocks %lX buffer at %lX\n", device, blknr, blkcnt, (ulong)buffer); ide_led (DEVICE_LED(device), 1); /* LED on */ diff --combined drivers/spi/kirkwood_spi.c index 135895f,54c4036..dfe542d --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@@ -27,6 -27,7 +27,7 @@@ #include #include #include + #include #include #include #include @@@ -106,6 -107,10 +107,10 @@@ int spi_cs_is_valid(unsigned int bus, u } #endif + void spi_init(void) + { + } + void spi_cs_activate(struct spi_slave *slave) { writel(readl(&spireg->ctrl) | KWSPI_IRQUNMASK, &spireg->ctrl); @@@ -122,7 -127,7 +127,7 @@@ int spi_xfer(struct spi_slave *slave, u unsigned int tmpdout, tmpdin; int tm, isread = 0; - debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n", slave->bus, slave->cs, dout, din, bitlen); if (flags & SPI_XFER_BEGIN) @@@ -158,7 -163,7 +163,7 @@@ isread = 1; tmpdin = readl(&spireg->din); debug - ("spi_xfer: din %08x..%08x read\n", + ("spi_xfer: din %p..%08x read\n", din, tmpdin); if (din) { diff --combined include/configs/efikamx.h index ce96b78,7e4b424..b507786 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@@ -79,7 -79,7 +79,7 @@@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT /* * Hardware drivers @@@ -124,11 -124,14 +124,14 @@@ #endif /* SPI PMIC */ - #define CONFIG_FSL_PMIC + #define CONFIG_PMIC + #define CONFIG_PMIC_SPI + #define CONFIG_PMIC_FSL #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS (0 | 120 << 8) #define CONFIG_FSL_PMIC_CLK 25000000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) + #define CONFIG_FSL_PMIC_BITLEN 32 #define CONFIG_RTC_MC13783 #endif diff --combined include/configs/mx31pdk.h index 044b766,b72f30b..2e5cde5 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@@ -70,11 -70,15 +70,15 @@@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - #define CONFIG_FSL_PMIC + /* PMIC Controller */ + #define CONFIG_PMIC + #define CONFIG_PMIC_SPI + #define CONFIG_PMIC_FSL #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 2 #define CONFIG_FSL_PMIC_CLK 1000000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) + #define CONFIG_FSL_PMIC_BITLEN 32 #define CONFIG_RTC_MC13783 /* allow to overwrite serial and ethaddr */ @@@ -102,7 -106,7 +106,7 @@@ */ #undef CONFIG_CMD_IMLS -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #define CONFIG_BOOTDELAY 3 diff --combined include/configs/mx35pdk.h index 6f42fc7,1707b4d..79bae56 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@@ -42,7 -42,7 +42,7 @@@ #define CONFIG_SYS_64BIT_VSPRINTF #define CONFIG_BOARD_EARLY_INIT_F -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_REVISION_TAG @@@ -69,8 -69,9 +69,9 @@@ /* * PMIC Configs */ - #define CONFIG_FSL_PMIC - #define CONFIG_FSL_PMIC_I2C + #define CONFIG_PMIC + #define CONFIG_PMIC_I2C + #define CONFIG_PMIC_FSL #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 /* diff --combined include/configs/mx51evk.h index fd7f4ce,0d4ceb3..028a842 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@@ -54,7 -54,7 +54,7 @@@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT /* * Hardware drivers @@@ -70,11 -70,15 +70,15 @@@ #define CONFIG_MXC_SPI - #define CONFIG_FSL_PMIC + /* PMIC Controller */ + #define CONFIG_PMIC + #define CONFIG_PMIC_SPI + #define CONFIG_PMIC_FSL #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) + #define CONFIG_FSL_PMIC_BITLEN 32 /* * MMC Configs diff --combined include/configs/mx53evk.h index 034fa87,97ae2f2..4703248 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@@ -44,7 -44,7 +44,7 @@@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART @@@ -59,8 -59,9 +59,9 @@@ #define CONFIG_SYS_I2C_SLAVE 0xfe /* PMIC Configs */ - #define CONFIG_FSL_PMIC - #define CONFIG_FSL_PMIC_I2C + #define CONFIG_PMIC + #define CONFIG_PMIC_I2C + #define CONFIG_PMIC_FSL #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 /* MMC Configs */ diff --combined include/configs/qong.h index 8c68d1e,f2a1e01..c61a9b3 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@@ -60,11 -60,14 +60,14 @@@ #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 - #define CONFIG_FSL_PMIC + #define CONFIG_PMIC + #define CONFIG_PMIC_SPI + #define CONFIG_PMIC_FSL #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 100000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) + #define CONFIG_FSL_PMIC_BITLEN 32 /* FPGA */ #define CONFIG_FPGA @@@ -135,7 -138,7 +138,7 @@@ #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_SPI -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #define CONFIG_BOOTDELAY 5 diff --combined include/configs/vision2.h index 56cbe3f,a2a9f3f..bee9e97 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@@ -39,7 -39,7 +39,7 @@@ #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2 @@@ -87,11 -87,14 +87,14 @@@ #define CONFIG_ENV_IS_IN_SPI_FLASH /* PMIC Controller */ - #define CONFIG_FSL_PMIC + #define CONFIG_PMIC + #define CONFIG_PMIC_SPI + #define CONFIG_PMIC_FSL #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE SPI_MODE_0 + #define CONFIG_FSL_PMIC_BITLEN 32 #define CONFIG_RTC_MC13783 /* @@@ -187,14 -190,15 +190,15 @@@ #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) #define PHYS_SDRAM_2 CSD1_BASE_ADDR #define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x90000000 - #define CONFIG_SYS_INIT_RAM_ADDR 0x1FFE8000 - - #define CONFIG_SYS_INIT_RAM_SIZE (64 * 1024) - #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR + #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + + #define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + #define CONFIG_BOARD_EARLY_INIT_F /* 166 MHz DDR RAM */