From: sivarv <sivarv@microsoft.com>
Date: Sat, 12 Nov 2016 00:41:16 +0000 (-0800)
Subject: Generate inc/dec [mem] instead of add/sub [mem], 1 for read-modify-write operations.
X-Git-Tag: accepted/tizen/base/20180629.140029~3065^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8753709778f4282b16647946dfe61cfd8f8414e5;p=platform%2Fupstream%2Fcoreclr.git

Generate inc/dec [mem] instead of add/sub [mem], 1 for read-modify-write operations.
---

diff --git a/src/jit/codegenxarch.cpp b/src/jit/codegenxarch.cpp
index 36a6cf5..5e4153c 100644
--- a/src/jit/codegenxarch.cpp
+++ b/src/jit/codegenxarch.cpp
@@ -4533,6 +4533,22 @@ void CodeGen::genStoreInd(GenTreePtr node)
                     assert(rmwSrc == data->gtGetOp2());
                     genCodeForShiftRMW(storeInd);
                 }
+                else if (data->OperGet() == GT_ADD && rmwSrc->IsIntegralConst(1))
+                {
+                    // Generate inc [mem] instead of "add [mem], 1".
+                    // Note that we don't need to check for GT_SUB of -1 because
+                    // global morph would transform it to GT_ADD of 1.
+                    assert(rmwSrc->isContainedIntOrIImmed());
+                    getEmitter()->emitInsRMW(INS_inc, emitTypeSize(storeInd), storeInd);
+                }
+                else if (data->OperGet() == GT_ADD && rmwSrc->IsIntegralConst(-1))
+                {
+                    // Generate dec [mem] instead of "add [mem], -1".
+                    // Note that we don't need to check for GT_SUB of 1 because
+                    // global morph would transform it to GT_ADD of -1.
+                    assert(rmwSrc->isContainedIntOrIImmed());
+                    getEmitter()->emitInsRMW(INS_dec, emitTypeSize(storeInd), storeInd);
+                }
                 else
                 {
                     // generate code for remaining binary RMW memory ops like add/sub/and/or/xor