From: Topi Pohjolainen <topi.pohjolainen@intel.com>
Date: Wed, 9 Dec 2015 12:44:21 +0000 (+0200)
Subject: i965/gen9: Prepare surface state setup for lossless compression
X-Git-Tag: upstream/17.1.0~10009
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=874c5f05dbc8eca2d14a14f32fdd964808c53b7e;p=platform%2Fupstream%2Fmesa.git

i965/gen9: Prepare surface state setup for lossless compression

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression (intel_miptree_is_lossless_compressed()).
v3 (Ben): Do not set fast claer state in surface state setup.
          Moved into brw_postdraw_set_buffers_need_resolve()
          using a separate patch.
v4: Support for blorp
v5 (Ben): Re-use gen8_get_aux_mode()

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 4696faf..fce510c 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -656,6 +656,7 @@
 #define GEN8_SURFACE_AUX_MODE_MCS               1
 #define GEN8_SURFACE_AUX_MODE_APPEND            2
 #define GEN8_SURFACE_AUX_MODE_HIZ               3
+#define GEN9_SURFACE_AUX_MODE_CCS_E             5
 
 /* Surface state DW7 */
 #define GEN9_SURFACE_RT_COMPRESSION_SHIFT       30
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c
index 5cd070f..05ef54c 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -77,7 +77,7 @@ gen8_blorp_emit_surface_state(struct brw_context *brw,
       surf[6] = SET_FIELD(surface->mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
                 SET_FIELD((surface->mt->mcs_mt->pitch / 128) - 1,
                           GEN8_SURFACE_AUX_PITCH) |
-                GEN8_SURFACE_AUX_MODE_MCS;
+                gen8_get_aux_mode(brw, mt);
    } else {
       surf[6] = 0;
    }
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 4f9a6e9..4b9896f 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -216,6 +216,9 @@ gen8_get_aux_mode(const struct brw_context *brw,
    if (brw->gen >= 9 || mt->num_samples == 1)
       assert(mt->halign == 16);
 
+   if (intel_miptree_is_lossless_compressed(brw, mt))
+      return GEN9_SURFACE_AUX_MODE_CCS_E;
+
    return GEN8_SURFACE_AUX_MODE_MCS;
 }