From: Vladimir Oltean Date: Thu, 15 Dec 2022 13:56:35 +0000 (+0200) Subject: arm64: dts: ls1028a: declare cache-coherent page table walk feature for IOMMU X-Git-Tag: v6.6.17~5549^2~30^2~38 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8720913f8402e55a0b4da4bfc528c320925760d7;p=platform%2Fkernel%2Flinux-rpi.git arm64: dts: ls1028a: declare cache-coherent page table walk feature for IOMMU The SMMUv2 driver for MMU-500 reads the ARM_SMMU_GR0_ID0 register at probe time and tries to determine based on the CTTW (Coherent Translation Table Walk) bit whether this feature is supported. Unfortunately, it looks like the SMMU integration in the NXP LS1028A has wrongly tied the cfg_cttw signal to 0, even though the SoC documentation specifies that "The SMMU supports cache coherency for page table walks and DVM transactions for page table cache maintenance operations." Device tree provides the option of overriding the ID register via the dma-coherent property since commit bae2c2d421cd ("iommu/arm-smmu: Sort out coherency"), and that's what we do here. Telling struct io_pgtable_cfg that the SMMU page table walks are coherent with the CPU caches brings performance benefits, because it avoids certain operations such as __arm_lpae_sync_pte() for PTE updates. Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/ Suggested-by: Robin Murphy Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 1b33cab..9e50976 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -713,6 +713,7 @@ reg = <0 0x5000000 0 0x800000>; #global-interrupts = <8>; #iommu-cells = <1>; + dma-coherent; stream-match-mask = <0x7c00>; /* global secure fault */ interrupts = ,