From: pinskia <pinskia@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue, 13 Sep 2005 21:50:47 +0000 (+0000)
Subject: 2005-09-13  Andrew Pinski  <pinskia@physics.uc.edu>
X-Git-Tag: upstream/4.9.2~58653
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=868685be659d9d69de56311853021bb46acf1ff2;p=platform%2Fupstream%2Flinaro-gcc.git

2005-09-13  Andrew Pinski  <pinskia@physics.uc.edu>

        * config/rs6000/darwin.md (movdf_low_si): Mark the outgoing r constraint
        as early clobber.  Rewrite so the PIC register is not implicitly used.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@104241 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ea56ce6..bde5734 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2005-09-13  Andrew Pinski  <pinskia@physics.uc.edu>
+
+	* config/rs6000/darwin.md (movdf_low_si): Mark the outgoing r constraint
+	as early clobber.  Rewrite so the PIC register is not implicitly used.
+
 2005-09-13  Volker Reichelt  <reichelt@igpm.rwth-aachen.de>
 
 	* tree.c (annotate_with_file_line): Compare line numbers before
diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md
index 5dfa01a..0732817 100644
--- a/gcc/config/rs6000/darwin.md
+++ b/gcc/config/rs6000/darwin.md
@@ -28,7 +28,7 @@ Boston, MA 02110-1301, USA.  */
   [(set_attr "length" "4")])
 
 (define_insn "movdf_low_si"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!&r")
         (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
                            (match_operand 2 "" ""))))]
   "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
@@ -40,27 +40,15 @@ Boston, MA 02110-1301, USA.  */
 	return \"lfd %0,lo16(%2)(%1)\";
       case 1:
 	{
-	  rtx operands2[4];
-	  operands2[0] = operands[0];
-	  operands2[1] = operands[1];
-	  operands2[2] = operands[2];
 	  if (TARGET_POWERPC64 && TARGET_32BIT)
 	    /* Note, old assemblers didn't support relocation here.  */
 	    return \"ld %0,lo16(%2)(%1)\";
 	  else
-	  {
-	    operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
-	    output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
-#if TARGET_MACHO
-	    if (MACHO_DYNAMIC_NO_PIC_P)
-	      output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
-	    else
-	    /* We cannot rely on ha16(low half)==ha16(high half), alas,
-	       although in practice it almost always is.  */
-	    output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
-#endif
-	    return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
-	  }
+	    {
+	      output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
+	      output_asm_insn (\"{cal|la} %L0,lo16(%2)(%1)\", operands);
+	      return (\"{l|lwz} %L0,4(%L0)\");
+	    }
 	}
       default:
 	gcc_unreachable ();