From: William Qiu <william.qiu@starfivetech.com>
Date: Thu, 2 Mar 2023 08:42:57 +0000 (+0800)
Subject: riscv: dts: starfive: jh7110: Add qspi controller node
X-Git-Tag: accepted/tizen/unified/riscv/20230718.024919~186
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8605a5169312fc34d42129a8dccd2e80321efb1e;p=platform%2Fkernel%2Flinux-starfive.git

riscv: dts: starfive: jh7110: Add qspi controller node

Add the quad spi controller node for the Starfive JH7110 SoC.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 1a16f3bc4cbc..5ab159813ad5 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -486,6 +486,50 @@
 			status = "disabled";
 		};
 
+		qspi: spi@13010000 {
+			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x13010000 0x0 0x10000
+			       0x0 0x21000000 0x0 0x400000>;
+			interrupts = <25>;
+			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
+			resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+				 <&syscrg JH7110_SYSRST_QSPI_AHB>,
+				 <&syscrg JH7110_SYSRST_QSPI_REF>;
+			reset-names = "qspi", "qspi-ocp", "rstc_ref";
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x0>;
+
+			nor_flash: nor-flash@0 {
+				compatible = "jedec,spi-nor";
+				reg=<0>;
+				cdns,read-delay = <5>;
+				spi-max-frequency = <12000000>;
+				cdns,tshsl-ns = <1>;
+				cdns,tsd2d-ns = <1>;
+				cdns,tchsh-ns = <1>;
+				cdns,tslch-ns = <1>;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					spl@0 {
+						reg = <0x0 0x20000>;
+					};
+					uboot@100000 {
+						reg = <0x100000 0x300000>;
+					};
+					data@f00000 {
+						reg = <0xf00000 0x100000>;
+					};
+				};
+			};
+		};
+
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;