From: Loic Poulain Date: Thu, 31 Mar 2022 10:39:37 +0000 (+0200) Subject: imx8ulp: clock: Fix lcd clock algo X-Git-Tag: v2022.07~90^2~62 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=85d0580e684c74dcb0a90aa0c010006cda40af44;p=platform%2Fkernel%2Fu-boot.git imx8ulp: clock: Fix lcd clock algo The div loop uses reassign and reuse parent_rate, which causes the parent rate reference to be wrong after the first loop, the resulting clock becomes incorrect for div != 1. Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock") Signed-off-by: Loic Poulain Reviewed-by: Peng Fan --- diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 3e71a4f..3e88f46 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -440,10 +440,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) debug("PLL4 rate %ukhz\n", pll4_rate); for (pfd = 12; pfd <= 35; pfd++) { - parent_rate = pll4_rate; - parent_rate = parent_rate * 18 / pfd; - for (div = 1; div <= 64; div++) { + parent_rate = pll4_rate; + parent_rate = parent_rate * 18 / pfd; parent_rate = parent_rate / div; for (pcd = 0; pcd < 8; pcd++) {