From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri, 22 Oct 2010 13:59:29 +0000 (+0100)
Subject: agp/intel: Restore valid PTE bit for Sandybridge after bdd3072
X-Git-Tag: upstream/snapshot3+hdmi~12619^2~14^2~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git

agp/intel: Restore valid PTE bit for Sandybridge after bdd3072

In cleaning up the mask functions in bdd3072, the setting of the PTE
valid bit was dropped for Sandybridge.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0c8ff6d..6b6760e 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1211,13 +1211,13 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
 	u32 pte_flags;
 
 	if (type_mask == AGP_USER_UNCACHED_MEMORY)
-		pte_flags = GEN6_PTE_UNCACHED;
+		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
 	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
-		pte_flags = GEN6_PTE_LLC;
+		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
 		if (gfdt)
 			pte_flags |= GEN6_PTE_GFDT;
 	} else { /* set 'normal'/'cached' to LLC by default */
-		pte_flags = GEN6_PTE_LLC_MLC;
+		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
 		if (gfdt)
 			pte_flags |= GEN6_PTE_GFDT;
 	}