From: Fangrui Song Date: Thu, 2 Apr 2020 05:09:28 +0000 (-0700) Subject: [PPCInstPrinter] Change B to print the target address in hexadecimal form X-Git-Tag: llvmorg-12-init~10364 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=85adce3d73589adc5f6ae486ebd035238fb20ac5;p=platform%2Fupstream%2Fllvm.git [PPCInstPrinter] Change B to print the target address in hexadecimal form Follow-up of D76591 and D76907 --- diff --git a/lld/test/ELF/ppc32-call-stub-nopic.s b/lld/test/ELF/ppc32-call-stub-nopic.s index 118b52a..272a8b2 100644 --- a/lld/test/ELF/ppc32-call-stub-nopic.s +++ b/lld/test/ELF/ppc32-call-stub-nopic.s @@ -47,8 +47,8 @@ ## These instructions are referenced by .plt entries. # CHECK: 10010200 <.glink>: -# CHECK-NEXT: b .+8 -# CHECK-NEXT: b .+4 +# CHECK-NEXT: b 0x10010208 +# CHECK-NEXT: b 0x10010208 ## PLTresolve ## Operands of lis & lwz: .got+4 = 0x10020070+4 = 65536*4098+700 diff --git a/lld/test/ELF/ppc32-call-stub-pic.s b/lld/test/ELF/ppc32-call-stub-pic.s index 1798746..b9e1979 100644 --- a/lld/test/ELF/ppc32-call-stub-pic.s +++ b/lld/test/ELF/ppc32-call-stub-pic.s @@ -107,11 +107,10 @@ # HEX: 0x0004036c 00010294 00010298 0001029c ## These instructions are referenced by .plt entries. -# PIE: 00010294 <.glink>: -# SHARED: 000102b4 <.glink>: -# CHECK-NEXT: b .+12 -# CHECK-NEXT: b .+8 -# CHECK-NEXT: b .+4 +# CHECK: [[#%x,GLINK:]] <.glink>: +# CHECK-NEXT: b 0x[[#%x,GLINK+12]] +# CHECK-NEXT: b 0x[[#%x,GLINK+12]] +# CHECK-NEXT: b 0x[[#%x,GLINK+12]] ## PLTresolve ## Operand of addi: 0x100a8-.glink = 24 diff --git a/lld/test/ELF/ppc32-canonical-plt.s b/lld/test/ELF/ppc32-canonical-plt.s index 027f2aa..f29e66e 100644 --- a/lld/test/ELF/ppc32-canonical-plt.s +++ b/lld/test/ELF/ppc32-canonical-plt.s @@ -57,9 +57,9 @@ # CHECK-NEXT: bctr ## The 3 b instructions are referenced by .plt entries. -# CHECK-NEXT: 1001025c: b .+12 -# CHECK-NEXT: b .+8 -# CHECK-NEXT: b .+4 +# CHECK-NEXT: 1001025c: b 0x10010268 +# CHECK-NEXT: b 0x10010268 +# CHECK-NEXT: b 0x10010268 ## PLTresolve of 64 bytes is at the end. ## Operands of addis & addi: -0x1001025c = 65536*-4097-604 diff --git a/lld/test/ELF/ppc32-local-branch.s b/lld/test/ELF/ppc32-local-branch.s index 526bea6..95099df 100644 --- a/lld/test/ELF/ppc32-local-branch.s +++ b/lld/test/ELF/ppc32-local-branch.s @@ -7,10 +7,10 @@ ## R_PPC_REL24 and R_PPC_PLTREL24 are converted to PC relative relocations if the ## symbol is non-preemptable. The addend of R_PPC_PLTREL24 should be ignored. -# CHECK: <_start>: -# CHECK-NEXT: b .+12 -# CHECK-NEXT: b .+8 -# CHECK-NEXT: b .+4 +# CHECK: [[#%x,ADDR:]] <_start>: +# CHECK-NEXT: b 0x[[#%x,ADDR+12]] +# CHECK-NEXT: b 0x[[#%x,ADDR+12]] +# CHECK-NEXT: b 0x[[#%x,ADDR+12]] # CHECK-EMPTY: # CHECK-NEXT: : diff --git a/lld/test/ELF/ppc32-reloc-rel.s b/lld/test/ELF/ppc32-reloc-rel.s index b2bd0a4..fefeeba 100644 --- a/lld/test/ELF/ppc32-reloc-rel.s +++ b/lld/test/ELF/ppc32-reloc-rel.s @@ -13,7 +13,7 @@ b 1f 1: # CHECK-LABEL: section .R_PPC_REL24: -# CHECK: b .+4 +# CHECK: b 0x100100bc .section .R_PPC_REL32,"ax",@progbits .long 1f - . @@ -25,10 +25,10 @@ b 1f@PLT+32768 1: # CHECK-LABEL: section .R_PPC_PLTREL24: -# CHECK: b .+4 +# CHECK: b 0x100100c4 .section .R_PPC_LOCAL24PC,"ax",@progbits b 1f@local 1: # CHECK-LABEL: section .R_PPC_LOCAL24PC: -# CHECK: b .+4 +# CHECK: b 0x100100c8 diff --git a/lld/test/ELF/ppc64-call-reach.s b/lld/test/ELF/ppc64-call-reach.s index b88b146..5f0e2dc 100644 --- a/lld/test/ELF/ppc64-call-reach.s +++ b/lld/test/ELF/ppc64-call-reach.s @@ -59,15 +59,15 @@ test: # thunks. # CHECK-LABEL: test # CHECK: 10010014: bl 0x12010010 -# CHECK: 10010024: b .+33554428 +# CHECK: 10010024: b 0x12010020 # NEGOFFSET-LABEL: test # NEGOFFSET: 10010014: bl 0xe010014 -# NEGOFFSET: 10010024: b .+33554432 +# NEGOFFSET: 10010024: b 0xe010024 # THUNK-LABEL: : # THUNK: 10010014: bl 0x10010028 -# THUNK: 10010024: b .+20 +# THUNK: 10010024: b 0x10010038 # .branch_lt[0] # THUNK-LABEL: <__long_branch_callee>: diff --git a/lld/test/ELF/ppc64-reloc-rel.s b/lld/test/ELF/ppc64-reloc-rel.s index ea7367f..e086cad 100644 --- a/lld/test/ELF/ppc64-reloc-rel.s +++ b/lld/test/ELF/ppc64-reloc-rel.s @@ -34,7 +34,7 @@ rel16: .section .R_PPC64_REL24,"ax",@progbits b rel16 # CHECK-LABEL: Disassembly of section .R_PPC64_REL24: -# CHECK: b .+67108840 +# CHECK: 100101b0: b 0x10010198 .section .REL32_AND_REL64,"ax",@progbits .cfi_startproc diff --git a/lld/test/ELF/ppc64-toc-restore.s b/lld/test/ELF/ppc64-toc-restore.s index ca5df74..dec7609 100644 --- a/lld/test/ELF/ppc64-toc-restore.s +++ b/lld/test/ELF/ppc64-toc-restore.s @@ -52,7 +52,7 @@ _diff_object: noretbranch: b bar_local // CHECK-LABEL: : -// CHECK: 100102e0: b .+67108832 +// CHECK-NEXT: 100102e0: b 0x100102c0 // CHECK-EMPTY: // This should come last to check the end-of-buffer condition. diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index d6e0bc2..74c6fd3 100644 --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -67,9 +67,9 @@ static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, return MCDisassembler::Success; } -static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder) { +static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, + uint64_t /*Address*/, + const void * /*Decoder*/) { int32_t Offset = SignExtend32<24>(Imm); Inst.addOperand(MCOperand::createImm(Offset)); return MCDisassembler::Success; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 3102b90..189dd77 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -750,7 +750,9 @@ def PPCDirectBrAsmOperand : AsmOperandClass { def directbrtarget : Operand { let PrintMethod = "printBranchOperand"; let EncoderMethod = "getDirectBrEncoding"; + let DecoderMethod = "decodeDirectBrTarget"; let ParserMatchClass = PPCDirectBrAsmOperand; + let OperandType = "OPERAND_PCREL"; } def absdirectbrtarget : Operand { let PrintMethod = "printAbsBranchOperand"; @@ -776,7 +778,7 @@ def abscondbrtarget : Operand { def calltarget : Operand { let PrintMethod = "printBranchOperand"; let EncoderMethod = "getDirectBrEncoding"; - let DecoderMethod = "DecodePCRel24BranchTarget"; + let DecoderMethod = "decodeDirectBrTarget"; let ParserMatchClass = PPCDirectBrAsmOperand; let OperandType = "OPERAND_PCREL"; } diff --git a/llvm/test/CodeGen/PowerPC/alignlongjumptest.mir b/llvm/test/CodeGen/PowerPC/alignlongjumptest.mir index 56ddb2d..314844a 100644 --- a/llvm/test/CodeGen/PowerPC/alignlongjumptest.mir +++ b/llvm/test/CodeGen/PowerPC/alignlongjumptest.mir @@ -71,12 +71,12 @@ body: | # Check for the long branch. # CHECK-LE: 08 00 82 4{{[01]}} b{{[tf]}} 2, 0xc -# CHECK-LE-NEXT: fc 7f 00 48 b .+32764 +# CHECK-LE-NEXT: fc 7f 00 48 b 0x8004 # CHECK-LE-DAG: paddi 3, 3, 13, 0 # CHECK-LE-DAG: paddi 3, 3, 21, 0 # CHECK-LE: blr # CHECK-BE: 4{{[01]}} 82 00 08 b{{[tf]}} 2, 0xc -# CHECK-BE-NEXT: 48 00 7f fc b .+32764 +# CHECK-BE-NEXT: 48 00 7f fc b 0x8004 # CHECK-BE-DAG: paddi 3, 3, 13, 0 # CHECK-BE-DAG: paddi 3, 3, 21, 0 # CHECK-BE: blr diff --git a/llvm/test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s b/llvm/test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s index f04b7e5..bc0b682 100644 --- a/llvm/test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s +++ b/llvm/test/tools/llvm-objdump/ELF/PowerPC/branch-offset.s @@ -19,9 +19,9 @@ bl: bl .+4 # CHECK-LABEL: : -# CHECK-NEXT: b .+67108860 -# CHECK-NEXT: b .+0 -# CHECK-NEXT: b .+4 +# CHECK-NEXT: b 0x8 +# CHECK-NEXT: b 0x10 +# CHECK-NEXT: b 0x18 b: b .-4