From: Marek Olšák Date: Thu, 5 May 2022 17:57:49 +0000 (-0400) Subject: amd: replace num_rings[type] with ip[type].num_queues X-Git-Tag: upstream/22.3.5~9239 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=85aa067d0fbb49c234d33cdde03e4a107a85c798;p=platform%2Fupstream%2Fmesa.git amd: replace num_rings[type] with ip[type].num_queues Reviewed-by: Samuel Pitoiset Part-of: --- diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 4eefd1c..2eaf072 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -983,15 +983,15 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, assert(util_is_power_of_two_or_zero(dma.available_rings + 1)); assert(util_is_power_of_two_or_zero(compute.available_rings + 1)); - info->num_rings[AMD_IP_GFX] = util_bitcount(gfx.available_rings); - info->num_rings[AMD_IP_COMPUTE] = util_bitcount(compute.available_rings); - info->num_rings[AMD_IP_SDMA] = util_bitcount(dma.available_rings); - info->num_rings[AMD_IP_UVD] = util_bitcount(uvd.available_rings); - info->num_rings[AMD_IP_VCE] = util_bitcount(vce.available_rings); - info->num_rings[AMD_IP_UVD_ENC] = util_bitcount(uvd_enc.available_rings); - info->num_rings[AMD_IP_VCN_DEC] = util_bitcount(vcn_dec.available_rings); - info->num_rings[AMD_IP_VCN_ENC] = util_bitcount(vcn_enc.available_rings); - info->num_rings[AMD_IP_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings); + info->ip[AMD_IP_GFX].num_queues = util_bitcount(gfx.available_rings); + info->ip[AMD_IP_COMPUTE].num_queues = util_bitcount(compute.available_rings); + info->ip[AMD_IP_SDMA].num_queues = util_bitcount(dma.available_rings); + info->ip[AMD_IP_UVD].num_queues = util_bitcount(uvd.available_rings); + info->ip[AMD_IP_VCE].num_queues = util_bitcount(vce.available_rings); + info->ip[AMD_IP_UVD_ENC].num_queues = util_bitcount(uvd_enc.available_rings); + info->ip[AMD_IP_VCN_DEC].num_queues = util_bitcount(vcn_dec.available_rings); + info->ip[AMD_IP_VCN_ENC].num_queues = util_bitcount(vcn_enc.available_rings); + info->ip[AMD_IP_VCN_JPEG].num_queues = util_bitcount(vcn_jpeg.available_rings); /* This is "align_mask" copied from the kernel, maximums of all IP versions. */ info->ib_pad_dw_mask[AMD_IP_GFX] = 0xff; @@ -1379,16 +1379,16 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " clock_crystal_freq = %i KHz\n", info->clock_crystal_freq); fprintf(f, "Features:\n"); + fprintf(f, " ip[AMD_IP_GFX].num_queues = %i\n", info->ip[AMD_IP_GFX].num_queues); + fprintf(f, " ip[AMD_IP_SDMA].num_queues = %i\n", info->ip[AMD_IP_SDMA].num_queues); + fprintf(f, " ip[AMD_IP_COMPUTE].num_queues = %u\n", info->ip[AMD_IP_COMPUTE].num_queues); + fprintf(f, " ip[AMD_IP_UVD].num_queues = %i\n", info->ip[AMD_IP_UVD].num_queues); + fprintf(f, " ip[AMD_IP_VCE].num_queues = %i\n", info->ip[AMD_IP_VCE].num_queues); + fprintf(f, " ip[AMD_IP_UVD_ENC].num_queues = %i\n", info->ip[AMD_IP_UVD_ENC].num_queues); + fprintf(f, " ip[AMD_IP_VCN_DEC].num_queues = %i\n", info->ip[AMD_IP_VCN_DEC].num_queues); + fprintf(f, " ip[AMD_IP_VCN_ENC].num_queues = %i\n", info->ip[AMD_IP_VCN_ENC].num_queues); + fprintf(f, " ip[AMD_IP_VCN_JPEG].num_queues = %i\n", info->ip[AMD_IP_VCN_JPEG].num_queues); fprintf(f, " has_graphics = %i\n", info->has_graphics); - fprintf(f, " num_rings[AMD_IP_GFX] = %i\n", info->num_rings[AMD_IP_GFX]); - fprintf(f, " num_rings[AMD_IP_SDMA] = %i\n", info->num_rings[AMD_IP_SDMA]); - fprintf(f, " num_rings[AMD_IP_COMPUTE] = %u\n", info->num_rings[AMD_IP_COMPUTE]); - fprintf(f, " num_rings[AMD_IP_UVD] = %i\n", info->num_rings[AMD_IP_UVD]); - fprintf(f, " num_rings[AMD_IP_VCE] = %i\n", info->num_rings[AMD_IP_VCE]); - fprintf(f, " num_rings[AMD_IP_UVD_ENC] = %i\n", info->num_rings[AMD_IP_UVD_ENC]); - fprintf(f, " num_rings[AMD_IP_VCN_DEC] = %i\n", info->num_rings[AMD_IP_VCN_DEC]); - fprintf(f, " num_rings[AMD_IP_VCN_ENC] = %i\n", info->num_rings[AMD_IP_VCN_ENC]); - fprintf(f, " num_rings[AMD_IP_VCN_JPEG] = %i\n", info->num_rings[AMD_IP_VCN_JPEG]); fprintf(f, " has_clear_state = %u\n", info->has_clear_state); fprintf(f, " has_distributed_tess = %u\n", info->has_distributed_tess); fprintf(f, " has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 9d4fb33..abf46f3 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -42,6 +42,10 @@ extern "C" { struct amdgpu_gpu_info; +struct amd_ip_info { + uint8_t num_queues; +}; + struct radeon_info { /* PCI info: domain:bus:dev:func */ uint32_t pci_domain; @@ -63,8 +67,8 @@ struct radeon_info { uint32_t clock_crystal_freq; /* Features. */ + struct amd_ip_info ip[AMD_NUM_IP_TYPES]; bool has_graphics; /* false if the chip is compute-only */ - uint32_t num_rings[AMD_NUM_IP_TYPES]; uint32_t ib_pad_dw_mask[AMD_NUM_IP_TYPES]; bool has_clear_state; bool has_distributed_tess; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index aab0571..2b32230 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -583,7 +583,7 @@ radv_physical_device_init_queue_table(struct radv_physical_device *pdevice) for (unsigned i = 1; i < RADV_MAX_QUEUE_FAMILIES; i++) pdevice->vk_queue_to_radv[i] = RADV_MAX_QUEUE_FAMILIES + 1; - if (pdevice->rad_info.num_rings[AMD_IP_COMPUTE] > 0 && + if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) { pdevice->vk_queue_to_radv[idx] = RADV_QUEUE_COMPUTE; idx++; @@ -2416,7 +2416,7 @@ radv_get_physical_device_queue_family_properties(struct radv_physical_device *pd { int num_queue_families = 1; int idx; - if (pdevice->rad_info.num_rings[AMD_IP_COMPUTE] > 0 && + if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) num_queue_families++; @@ -2440,13 +2440,13 @@ radv_get_physical_device_queue_family_properties(struct radv_physical_device *pd idx++; } - if (pdevice->rad_info.num_rings[AMD_IP_COMPUTE] > 0 && + if (pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues > 0 && !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) { if (*pCount > idx) { *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties){ .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT | VK_QUEUE_SPARSE_BINDING_BIT, - .queueCount = pdevice->rad_info.num_rings[AMD_IP_COMPUTE], + .queueCount = pdevice->rad_info.ip[AMD_IP_COMPUTE].num_queues, .timestampValidBits = 64, .minImageTransferGranularity = (VkExtent3D){1, 1, 1}, }; diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c index 0ca4bf2..2e8ca6d 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c @@ -56,8 +56,8 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd) return false; } - ws->info.num_rings[AMD_IP_SDMA] = MIN2(ws->info.num_rings[AMD_IP_SDMA], MAX_RINGS_PER_TYPE); - ws->info.num_rings[AMD_IP_COMPUTE] = MIN2(ws->info.num_rings[AMD_IP_COMPUTE], MAX_RINGS_PER_TYPE); + ws->info.ip[AMD_IP_SDMA].num_queues = MIN2(ws->info.ip[AMD_IP_SDMA].num_queues, MAX_RINGS_PER_TYPE); + ws->info.ip[AMD_IP_COMPUTE].num_queues = MIN2(ws->info.ip[AMD_IP_COMPUTE].num_queues, MAX_RINGS_PER_TYPE); ws->use_ib_bos = ws->info.chip_class >= GFX7; return true; diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c index fda2224..8d360fc 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.c +++ b/src/gallium/drivers/r600/r600_pipe_common.c @@ -636,7 +636,7 @@ bool r600_common_context_init(struct r600_common_context *rctx, if (!rctx->ctx) return false; - if (rscreen->info.num_rings[AMD_IP_SDMA] && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) { + if (rscreen->info.ip[AMD_IP_SDMA].num_queues && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) { rctx->ws->cs_create(&rctx->dma.cs, rctx->ctx, AMD_IP_SDMA, r600_flush_dma_ring, rctx, false); rctx->dma.flush = r600_flush_dma_ring; @@ -1294,8 +1294,8 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory); printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2); printf("uvd_decode = %u\n", rscreen->info.has_video_hw.uvd_decode); - printf("num_rings[AMD_IP_SDMA] = %i\n", rscreen->info.num_rings[AMD_IP_SDMA]); - printf("num_rings[AMD_IP_COMPUTE] = %u\n", rscreen->info.num_rings[AMD_IP_COMPUTE]); + printf("ip[AMD_IP_SDMA] = %i\n", rscreen->info.ip[AMD_IP_SDMA].num_queues); + printf("ip[AMD_IP_COMPUTE] = %u\n", rscreen->info.ip[AMD_IP_COMPUTE].num_queues); printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version); printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version); printf("me_fw_version = %i\n", rscreen->info.me_fw_version); diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 029f5f4..b195da5 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -1195,7 +1195,7 @@ static bool is_noop_fence_dependency(struct amdgpu_cs *acs, * we need the parallelism between IBs for good performance. */ if ((acs->ip_type == AMD_IP_GFX || - acs->ws->info.num_rings[acs->ip_type] == 1) && + acs->ws->info.ip[acs->ip_type].num_queues == 1) && !amdgpu_fence_is_syncobj(fence) && fence->ctx == acs->ctx && fence->fence.ip_type == cs->ib[IB_MAIN].ip_type) diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 0df473e..b32fe09 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -304,12 +304,12 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.has_dedicated_vram = true; } - ws->info.num_rings[AMD_IP_GFX] = 1; + ws->info.ip[AMD_IP_GFX].num_queues = 1; /* Check for dma */ - ws->info.num_rings[AMD_IP_SDMA] = 0; + ws->info.ip[AMD_IP_SDMA].num_queues = 0; /* DMA is disabled on R700. There is IB corruption and hangs. */ if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) { - ws->info.num_rings[AMD_IP_SDMA] = 1; + ws->info.ip[AMD_IP_SDMA].num_queues = 1; } /* Check for UVD and VCE */ @@ -321,7 +321,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, "UVD Ring working", &value)) { ws->info.has_video_hw.uvd_decode = value; - ws->info.num_rings[AMD_IP_UVD] = 1; + ws->info.ip[AMD_IP_UVD].num_queues = 1; } value = RADEON_CS_RING_VCE; @@ -331,7 +331,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION, "VCE FW version", &value)) { ws->info.vce_fw_version = value; - ws->info.num_rings[AMD_IP_VCE] = 1; + ws->info.ip[AMD_IP_VCE].num_queues = 1; ws->info.has_video_hw.vce_encode = true; } }