From: Dave Airlie <airlied@redhat.com>
Date: Mon, 23 Dec 2013 00:46:07 +0000 (+1000)
Subject: Merge tag 'drm-intel-next-2013-12-13' of git://people.freedesktop.org/~danvet/drm... 
X-Git-Tag: accepted/tizen/common/20141203.182822~672^2~44
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=859ae233cd0ee76b6143f948ba1cb6b0b4c342f8;p=platform%2Fkernel%2Flinux-arm64.git

Merge tag 'drm-intel-next-2013-12-13' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

- fbc1 improvements from Ville (pre-gm45).
- vlv forcewake improvements from Deepak S.
- Some corner-cases fixes from Mika for the context hang stat code.
- pc8 improvements and prep work for runtime D3 from Paulo, almost ready for
  primetime.
- gen2 dpll fixes from Ville.
- DSI improvements from Shobhit Kumar.
- A few smaller fixes and improvements all over.

[airlied: intel_ddi.c conflict fixed up]

* tag 'drm-intel-next-2013-12-13' of git://people.freedesktop.org/~danvet/drm-intel: (61 commits)
  drm/i915/bdw: Implement ff workarounds
  drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent
  drm/i915/bdw: Don't use forcewake needlessly
  drm/i915: Clear out old GT FIFO errors in intel_uncore_early_sanitize()
  drm/i915: dont call irq_put when irq test is on
  drm/i915: Rework the FBC interval/stall stuff a bit
  drm/i915: Enable FBC for all mobile gen2 and gen3 platforms
  drm/i915: FBC_CONTROL2 is gen4 only
  drm/i915: Gen2 FBC1 CFB pitch wants 32B units
  drm/i915: split intel_ddi_pll_mode_set in 2 pieces
  drm/i915: Fix timeout with missed interrupts in __wait_seqno
  drm/i915: touch VGA MSR after we enable the power well
  drm/i915: extract hsw_power_well_post_{enable, disable}
  drm/i915: remove i915_disable_vga_mem declaration
  drm/i915: Parametrize the dphy and other spec specific parameters
  drm/i915: Remove redundant DSI PLL enabling
  drm/i915: Reorganize the DSI enable/disable sequence
  drm/i915: Try harder to get best m, n, p values with minimal error
  drm/i915: Compute dsi_clk from pixel clock
  drm/i915: Use FLISDSI interface for band gap reset
  ...

Conflicts:
	drivers/gpu/drm/i915/intel_ddi.c
---

859ae233cd0ee76b6143f948ba1cb6b0b4c342f8
diff --cc drivers/gpu/drm/i915/intel_ddi.c
index c8382f5,cec06a5..d7d2683
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@@ -1165,10 -1235,9 +1235,9 @@@ static void intel_ddi_post_disable(stru
  	if (wait)
  		intel_wait_ddi_buf_idle(dev_priv, port);
  
 -	if (type == INTEL_OUTPUT_EDP) {
 +	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- 		ironlake_edp_panel_vdd_on(intel_dp);
 -
 +		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
  		ironlake_edp_panel_off(intel_dp);
  	}