From: danglin Date: Thu, 20 Aug 2009 01:36:11 +0000 (+0000) Subject: * pa.md (reload_inhi, reload_outhi, reload_inqi, reload_outqi): New X-Git-Tag: upstream/4.9.2~34191 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=853940d980cdf01e6068fdf32ee64cf69704330b;p=platform%2Fupstream%2Flinaro-gcc.git * pa.md (reload_inhi, reload_outhi, reload_inqi, reload_outqi): New patterns. * pa.c (emit_move_sequence): Check if address of operand1 is valid for mode mode of operand0 when doing secondary reload for SAR. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@150951 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3a6e261..3749881 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2009-08-19 John David Anglin + + * pa.md (reload_inhi, reload_outhi, reload_inqi, reload_outqi): New + patterns. + * pa.c (emit_move_sequence): Check if address of operand1 is valid + for mode mode of operand0 when doing secondary reload for SAR. + 2009-08-19 Jakub Jelinek PR middle-end/41123 diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index c5543ef..4355d0a 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -1619,7 +1619,7 @@ emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) /* D might not fit in 14 bits either; for such cases load D into scratch reg. */ if (GET_CODE (operand1) == MEM - && !memory_address_p (Pmode, XEXP (operand1, 0))) + && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0))) { /* We are reloading the address into the scratch register, so we want to make sure the scratch register is a full register. */ diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index a20f406..20f6444 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2740,6 +2740,40 @@ DONE; }") +;; Handle HImode input reloads requiring a general register as a +;; scratch register. +(define_expand "reload_inhi" + [(set (match_operand:HI 0 "register_operand" "=Z") + (match_operand:HI 1 "non_hard_reg_operand" "")) + (clobber (match_operand:HI 2 "register_operand" "=&r"))] + "" + " +{ + if (emit_move_sequence (operands, HImode, operands[2])) + DONE; + + /* We don't want the clobber emitted, so handle this ourselves. */ + emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + DONE; +}") + +;; Handle HImode output reloads requiring a general register as a +;; scratch register. +(define_expand "reload_outhi" + [(set (match_operand:HI 0 "non_hard_reg_operand" "") + (match_operand:HI 1 "register_operand" "Z")) + (clobber (match_operand:HI 2 "register_operand" "=&r"))] + "" + " +{ + if (emit_move_sequence (operands, HImode, operands[2])) + DONE; + + /* We don't want the clobber emitted, so handle this ourselves. */ + emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + DONE; +}") + (define_insn "" [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,Q,!*q,!r") @@ -2864,6 +2898,40 @@ DONE; }") +;; Handle QImode input reloads requiring a general register as a +;; scratch register. +(define_expand "reload_inqi" + [(set (match_operand:QI 0 "register_operand" "=Z") + (match_operand:QI 1 "non_hard_reg_operand" "")) + (clobber (match_operand:QI 2 "register_operand" "=&r"))] + "" + " +{ + if (emit_move_sequence (operands, QImode, operands[2])) + DONE; + + /* We don't want the clobber emitted, so handle this ourselves. */ + emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + DONE; +}") + +;; Handle QImode output reloads requiring a general register as a +;; scratch register. +(define_expand "reload_outqi" + [(set (match_operand:QI 0 "non_hard_reg_operand" "") + (match_operand:QI 1 "register_operand" "Z")) + (clobber (match_operand:QI 2 "register_operand" "=&r"))] + "" + " +{ + if (emit_move_sequence (operands, QImode, operands[2])) + DONE; + + /* We don't want the clobber emitted, so handle this ourselves. */ + emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + DONE; +}") + (define_insn "" [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,Q,!*q,!r")