From: Andrzej Hajda Date: Thu, 5 Feb 2015 08:42:29 +0000 (+0100) Subject: ARM: dts: exynos5420: add async-bridge clocks to disp1 power domain X-Git-Tag: submit/tizen/20150416.081342~97 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=84f6bbc19bcf9e3087f890eb2c5b516d83628e33;p=platform%2Fkernel%2Flinux-exynos.git ARM: dts: exynos5420: add async-bridge clocks to disp1 power domain FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER), therefore their clocks should be enabled during power domain switch. Signed-off-by: Andrzej Hajda --- diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c0e98cf3514f..55e38877350f 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -283,9 +283,11 @@ <&clock CLK_MOUT_SW_ACLK300>, <&clock CLK_MOUT_USER_ACLK300_DISP1>, <&clock CLK_MOUT_SW_ACLK400>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>; + <&clock CLK_MOUT_USER_ACLK400_DISP1>, + <&clock CLK_FIMD1>, <&clock CLK_MIXER>; clock-names = "oscclk", "pclk0", "clk0", - "pclk1", "clk1", "pclk2", "clk2"; + "pclk1", "clk1", "pclk2", "clk2", + "asb0", "asb1"; }; pinctrl_0: pinctrl@13400000 {