From: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
Date: Mon, 7 Mar 2016 14:30:45 +0000 (+0100)
Subject: EDAC, sb_edac: Fix logic when computing DIMM sizes on Xeon Phi
X-Git-Tag: v4.9.8~2579^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=83bdaad4d919722744ef1b726a9913ec36c6a430;p=platform%2Fkernel%2Flinux-rpi3.git

EDAC, sb_edac: Fix logic when computing DIMM sizes on Xeon Phi

Correct a typo introduced by

  d0cdf9003140 ("EDAC, sb_edac: Add Knights Landing (Xeon Phi gen 2) support")

As a result under some configurations DIMMs were not correctly
recognized. Problem affects only Xeon Phi architecture.

Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
Acked-by: Aristeu Rozanski <aris@redhat.com>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: lukasz.anaczkowski@intel.com
Link: http://lkml.kernel.org/r/1457361045-26221-1-git-send-email-hubert.chrzaniuk@intel.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---

diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index e438ee5..f5c6b97 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -1574,7 +1574,7 @@ static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
 				for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
 					if (knl_get_mc_route(target,
 						mc_route_reg[cha]) == channel
-						&& participants[channel]) {
+						&& !participants[channel]) {
 						participant_count++;
 						participants[channel] = 1;
 						break;